UC2842B/3B/4B/5B - UC3842B/3B/4B/5B
Figure 22: External Clock Synchronization.
VREF
8
4
R
BIAS
RT
CT
R
OSC
+
EXTERNAL
SYNC INPUT
2R
0.01µF
+
-
2
1
EA
47Ω
R
5
D95IN352
The diode clamp is required if the Sync amplitude is large enough to cause
the bottom side of CT to go more than 300mV below ground
Figure 23:
External Duty Cycle Clamp and Multi Unit Synchronization.
VREF
8
RA
RB
R
R
BIAS
OSC
8
4
5K
5K
5K
6
5
+
-
3
7
4
R
S
+
Q
2R
+
-
+
-
2
2
1
EA
C
R
1
NE555
5
TO ADDITIONAL
UCX84XAs
1.44
(RA + 2RB)C
RB
RA + 2RB
f =
Dmax
=
D95IN353
11/15