TDA7377
Normally the clip detector signalling produces a
low level at pin 10 that is shorter than that present
under faulty conditions; based on this assumption
Figure 26.
an interface circuitry to differentiate the informa-
tion is represented in the schematic of fig. 26.
TDA7377
PCB-LAYOUT GROUNDING (general rules)
The device has 2 distinct ground leads, P-GND
(POWER GROUND) and S-GND (SIGNAL
GROUND) which are practically disconnected
from each other at chip level. Proper operation re-
quires that P-GND and S-GND leads be con-
nected together on the PCB-layout by means of
reasonably low-resistance tracks.
As for the PCB-ground configuration, a star-like
arrangement whose center is represented by the
supply-filtering electrolytic capacitor ground is
highly advisable. In such context, at least 2 sepa-
rate paths have to be provided, one for P-GND
and one for S-GND. The correct ground assign-
ments are as follows:
STANDBY CAPACITOR, pin 7 (or any other
standby driving networks): on S-GND
SVR CAPACITOR (pin 6): on S-GND and to be
placed as close as possible to the device.
INPUT SIGNAL GROUND (from active/passive
signal processor stages): on S-GND.
SUPPLY FILTERING CAPACITORS (pins 3,13):
on P-GND. The (-) terminal of the electrolytic ca-
pacitor has to be directly tied to the battery (-) line
and this should represent the starting point for all
the ground paths.
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