STV0299B
1
PIN INFORMATION
(continued)
1.2 Pinout Description
Pin Number
SIGNAL INPUTS
50, 51
53, 54
1
2
9
5
17-18
19
38
SIGNAL OUPUTS
26-28-29-31, 33 to 36
24
22
21
20
D[7:0]
CLK_OUT
STR_OUT
D/P
ERROR
O
2
O
2
O
2
O
2
O
2
Output Data; D7 is DATA_OUT in Serial Mode
Output Byte Clock; or Bit Clock in Serial Mode
Output 1st byte Signal (synchro byte clock)
Data/Parity Signal
Output Error Signal. Set in case of uncorrectible packet.
IP, IN
QN, QP
CLK_IN/XTAL IN
XTAL OUT
AGC
AUX_CLK
OP0, OP1
LOCK/OP2
IP0
I
I
I
O
OD
3
O
2
O
2
O
2
I
Analog in Phase Component
Analog in Quadrature Component
Crystal Input or CLK_IN
Crystal Output
Control Signal to the Tuner
Programmable Output Port or Programmable Output Clock
Programmable Output Ports
Carrier Found or Data Found or Output Port
Input Port
Name
I/O
1
Description
FRONT END CONTROLS
I
2
C INTERFACE
14
12
OTHERS
59
60
37-43-44-45-46-61-62
58
3, 49, 52, 57
4, 47, 55
56
48
6-8-11-23-27-32-39-64
13-25
7-10-30-41-63
15
42
16
40
Note:
1
2
3
SCL
SDA
I
3
Serial Clock (I
2
C bus)
I/OD
3
Serial Data (I
2
C bus)
OD
3
Tuner Serial Clock (repeator) or Output Port
SCLT
SDAT
TEST
DIRCLK_DIS
V
SSA
V
DDA
V
TOP
V
BOT
V
SS
V
DD_3.3 V
V
DD
RESET
STDBY
F22/DiSEqC
DAC
I/OD
3
Tuner Serial Data (repeator) or Input/Output Port
I
I
S
S
S
S
S
S
S
I
I
O
2
O
2
Reserved for manufacturing tests; must be tied to V
SS
Sets the DIRCLK function at power on
Analog Ground
Analog 2.5 V Supply
ADC High Voltage Reference
ADC Low Voltage Reference
Ground
3.3 V Supply
2.5 V Supply
Reset, active at low level
Sets STDBY at power on
DiSEqC modulation, 22 kHz Tone, Programmable
Output Port
Programmable Digital to Analog Converter Output
The following abbreviations are used: I - Input; O - Output; OD - Open drain output.
3.3 V output levels.
5 V tolerant
5/36
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