STNRGPF01
STNRGPF01 control architecture
2
STNRGPF01 control architecture
The STNRGPF01 implements mixed signal (analog/digital) control. The inner current loop is
performed by hardware and the outer voltage loop is performed by a digital PI controller.
The device performs cascaded control for voltage and current loops to regulate the output
voltage by acting on the total average inductor current.
Figure 1. STNRGPF01 control scheme
Figure 1 shows the STNRGPF01 control scheme. As can be observed, the difference
between the output voltage feedback V
and reference V
is sent to a digital PI
out_fb
out_ref
controller, which calculates the peak of the input average total current i
section, green line).
. (internal digital
pk_ref
The PFC current reference is internally generated and is output from the I/O FFD block as
the PWM signal. After filtering it becomes the total average sinusoidal input current
reference i
for the inner current loop (external analog section, red line). The difference
tot_ref
between the current reference i
analog PI controller.
and the input current feedback i
is sent to the
tot_ref
tot_fb
DocID030377 Rev 2
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STMICROELECTRONICS [ ST ]
