STM8S207xx, STM8S208xx
Figure 12. f
Electrical characteristics
versus V
CPUmax
DD
fCPU [MHz]
24
FUNCTIONALITY GUARANTEED
@ TA -40 to 105 °C
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
16
12
8
FUNCTIONALITY
GUARANTEED
@ TA -40 to 125 °C
4
0
2.95
4.0
5.0
5.5
SUPPLY VOLTAGE [V]
Table 19. Operating conditions at power-up/power-down
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD rise time rate
VDD fall time rate
2(1)
2(1)
∞
∞
tVDD
µs/V
Reset release
delay
tTEMP
VIT+
VDD rising
1.7(1)
2.95
2.88
ms
V
Power-on reset
threshold
2.65
2.58
2.8
2.73
70
Brown-out reset
threshold
VIT-
V
Brown-out reset
hysteresis
VHYS(BOR)
mV
1. Guaranteed by design, not tested in production.
10.3.1
VCAP external capacitor
Stabilization for the main regulator is achieved connecting an external capacitor C
to the
EXT
V
pin. C
is specified in Table 18. Care should be taken to limit the series inductance
CAP
EXT
to less than 15 nH.
Figure 13. External capacitor C
EXT
ESR
C
ESL
Rleak
1. Legend: ESR is the equivalent series resistance and ESL is the equivalent inductance.
Doc ID 14733 Rev 9
57/103
STMICROELECTRONICS [ ST ]
