STM8S207xx, STM8S208xx
Option bytes
8
Option bytes
Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated block of the memory. Except for the
ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form
(OPTx) and a complemented one (NOPTx) for redundancy.
Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address
shown in Table 12: Option bytes below. Option bytes can also be modified ‘on the fly’ by the
application in IAP mode, except the ROP option that can only be modified in ICP mode (via
SWIM).
Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM
communication protocol and debug module user manual (UM0470) for information on SWIM
programming procedures.
Table 12. Option bytes
Option bits
Factory
default
setting
Option
name
Option
byte no.
Addr.
7
6
5
4
3
2
1
0
Read-out
4800h
protection
(ROP)
OPT0
ROP[7:0]
00h
4801h
4802h
4803h
OPT1
NOPT1
OPT2
UBC[7:0]
NUBC[7:0]
AFR3
00h
FFh
00h
User boot
code(UBC)
Alternate
function
remapping
(AFR)
AFR7
AFR6
AFR5
AFR4
AFR2
AFR1
AFR0
4804h
NOPT2
NAFR7
NAFR6
NAFR5
NAFR4
NAFR3
NAFR2
NAFR1
NAFR0
FFh
LSI
IWDG
_HW
WWDG
_HW
WWDG
_HALT
4805h
4806h
4807h
4808h
OPT3
Reserved
00h
FFh
00h
FFh
_EN
Watchdog
option
NLSI
_EN
NWWDG
_HW
NIWDG
_HW
NWWDG
_HALT
NOPT3
OPT4
Reserved
Reserved
Reserved
EXT
CLK
CKAWU
SEL
PRS
C1
PRS
C0
Clock option
NEXT
CLK
NCKAWUS
EL
NPR
SC1
NPR
SC0
NOPT4
4809h
480Ah
480Bh
480Ch
480Dh
480Eh
487Eh
487Fh
OPT5
HSECNT[7:0]
NHSECNT[7:0]
Reserved
00h
FFh
00h
FFh
00h
FFh
00h
FFh
HSE clock
startup
NOPT5
OPT6
Reserved
NOPT6
OPT7
Reserved
Reserved
Reserved
BL[7:0]
NBL[7:0]
Wait state
Flash wait
states
NOPT7
OPTBL
NOPTBL
Nwait state
Bootloader
Doc ID 14733 Rev 9
47/103
STMICROELECTRONICS [ ST ]
