List of tables
STM8S105xx
List of tables
Table 1. Device summary .........................................................................................................................1
Table 2. STM8S105xx access line features .............................................................................................9
Table 3. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers ..................................15
Table 4. TIM timer features ...................................................................................................................17
Table 5. Legend/abbreviations ..............................................................................................................21
Table 6. Pin description for STM8S105 microcontrollers .......................................................................25
Table 7. Flash, Data EEPROM and RAM boundary addresses ..........................................................108
Table 8. I/O port hardware register map ..............................................................................................113
Table 9. General hardware register map ................................................................................................33
Table 10. CPU/SWIM/debug module/interrupt controller registers ......................................................114
Table 11. Interrupt mapping ....................................................................................................................50
Table 12. Option bytes ..........................................................................................................................57
Table 13. Option byte description ...........................................................................................................53
Table 14. Description of alternate function remapping bits [7:0] of OPT2 ..............................................55
Table 15. Unique ID registers (96 bits) ...................................................................................................57
Table 16. Voltage characteristics ...........................................................................................................59
Table 17. Current characteristics ...........................................................................................................60
Table 18. Thermal characteristics ..........................................................................................................61
Table 19. General operating conditions .................................................................................................62
Table 20. Operating conditions at power-up/power-down ......................................................................63
Table 21. Total current consumption with code execution in run mode at VDD = 5 V .............................64
Table 22. Total current consumption with code execution in run mode at VDD = 3.3 V ..........................76
Table 23. Total current consumption in wait mode at VDD = 5 V ............................................................67
Table 24. Total current consumption in wait mode at VDD = 3.3 V .........................................................68
Table 25. Total current consumption in active halt mode at VDD = 5 V ..................................................68
Table 26. Total current consumption in active halt mode at VDD = 3.3 V ...............................................69
Table 27. Total current consumption in halt mode at VDD = 5 V .............................................................70
Table 28. Total current consumption in halt mode at VDD = 3.3 V ..........................................................71
Table 29. Wakeup times .........................................................................................................................71
Table 30. Total current consumption and timing in forced reset state ..................................................104
Table 31. Peripheral current consumption .............................................................................................72
Table 32. HSE user external clock characteristics .................................................................................76
Table 33. HSE oscillator characteristics .................................................................................................77
Table 34. HSI oscillator characteristics ..................................................................................................78
Table 35. LSI oscillator characteristics ...................................................................................................80
Table 36. RAM and hardware registers ..................................................................................................81
Table 37. Flash program memory/data EEPROM memory ....................................................................81
Table 38. I/O static characteristics .........................................................................................................82
Table 39. Output driving current (standard ports) ..................................................................................84
Table 40. Output driving current (true open drain ports) ........................................................................85
Table 41. Output driving current (high sink ports) ..................................................................................85
Table 42. NRST pin characteristics ........................................................................................................91
Table 43. SPI characteristics ..................................................................................................................94
Table 44. I2C characteristics ..................................................................................................................97
Table 45. ADC characteristics ................................................................................................................98
Table 46. ADC accuracy with RAIN < 10 kΩ , VDDA= 5 V .......................................................................99
Table 47. ADC accuracy with RAIN < 10 kΩ RAIN, VDDA = 3.3 V ..........................................................100
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