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STM8S003F3P6 参数 Datasheet PDF下载

STM8S003F3P6图片预览
型号: STM8S003F3P6
PDF下载: 下载PDF文件 查看货源
内容描述: 价值线, 16兆赫STM8S 8位MCU , 8 KB闪存, 128字节的数据EEPROM , 10位ADC , 3个定时器, UART , SPI , I& SUP2 ; ç [Value line, 16 MHz STM8S 8-bit MCU, 8 Kbytes Flash, 128 bytes data EEPROM, 10-bit ADC, 3 timers, UART, SPI, I²C]
分类和应用: 闪存可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 99 页 / 952 K
品牌: STMICROELECTRONICS [ ST ]
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List of figures  
STM8S003K3 STM8S003F3  
List of figures  
Figure 1. Block diagram ...........................................................................................................................9  
Figure 2. Flash memory organization ....................................................................................................12  
Figure 3. STM8S003K3 LQFP32 pinout ................................................................................................18  
Figure 4. STM8S003F3 TSSOP20 pinout ..............................................................................................21  
Figure 5. STM8S003F3 UFQFPN20-pin pinout .....................................................................................22  
Figure 6. Memory map ...........................................................................................................................25  
Figure 7. Pin loading conditions .............................................................................................................46  
Figure 8. Pin input voltage .....................................................................................................................47  
Figure 9. fCPUmax versus VDD ................................................................................................................50  
Figure 10. External capacitor CEXT .......................................................................................................50  
Figure 11. Typ IDD(RUN) vs. VDD HSE user external clock, fCPU = 16 MHz .............................................58  
Figure 12. Typ IDD(RUN) vs. fCPU HSE user external clock, VDD = 5 V ....................................................58  
Figure 13. Typ IDD(RUN) vs. VDD HSI RC osc, fCPU = 16 MHz .................................................................59  
Figure 14. Typ IDD(WFI) vs. VDD HSE user external clock, fCPU = 16 MHz ..............................................59  
Figure 15. Typ IDD(WFI) vs. fCPU HSE user external clock, VDD = 5 V .....................................................60  
Figure 16. Typ IDD(WFI) vs. VDD HSI RC osc, fCPU = 16 MHz .................................................................60  
Figure 17. HSE external clock source ....................................................................................................61  
Figure 18. HSE oscillator circuit diagram ...............................................................................................62  
Figure 19. Typical HSI frequency variation vs VDD @ 4 temperatures ..................................................63  
Figure 20. Typical LSI frequency variation vs VDD @ 4 temperatures ...................................................64  
Figure 21. Typical VIL and VIH vs VDD @ 4 temperatures ......................................................................67  
Figure 22. Typical pull-up resistance vs VDD @ 4 temperatures ............................................................67  
Figure 23. Typical pull-up current vs VDD @ 4 temperatures .................................................................68  
Figure 24. Typ. VOL @ VDD = 5 V (standard ports) ................................................................................70  
Figure 25. Typ. VOL @ VDD = 3.3 V (standard ports) .............................................................................70  
Figure 26. Typ. VOL @ VDD = 5 V (true open drain ports) ......................................................................71  
Figure 27. Typ. VOL @ VDD = 3.3 V (true open drain ports) ...................................................................71  
Figure 28. Typ. VOL @ VDD = 5 V (high sink ports) ................................................................................72  
Figure 29. Typ. VOL @ VDD = 3.3 V (high sink ports) .............................................................................72  
Figure 30. Typ. VDD - VOH@ VDD = 5 V (standard ports) .......................................................................73  
Figure 31. Typ. VDD - VOH @ VDD = 3.3 V (standard ports) ...................................................................73  
Figure 32. Typ. VDD - VOH@ VDD = 5 V (high sink ports) .......................................................................74  
Figure 33. Typ. VDD - VOH@ VDD = 3.3 V (high sink ports) ....................................................................74  
Figure 34. Typical NRST VIL and VIH vs VDD @ 4 temperatures ...........................................................76  
Figure 35. Typical NRST pull-up resistance vs VDD @ 4 temperatures .................................................76  
Figure 36. Typical NRST pull-up current vs VDD @ 4 temperatures ......................................................77  
Figure 37. Recommended reset pin protection ......................................................................................77  
Figure 38. SPI timing diagram - slave mode and CPHA = 0 ..................................................................79  
Figure 39. SPI timing diagram - slave mode and CPHA = 1 ..................................................................79  
Figure 40. SPI timing diagram - master mode(1) ...................................................................................80  
Figure 41. Typical application with I2C bus and timing diagram ............................................................84  
Figure 42. ADC accuracy characteristics ...............................................................................................84  
Figure 43. Typical application with ADC ................................................................................................85  
Figure 44. 32-pin low profile quad flat package (7 x 7) ..........................................................................89  
Figure 45. 20-pin, 4.40 mm body, 0.65 mm pitch ...................................................................................90  
Figure 46. 20-lead ultra thin fine pitch quad flat no-lead package outline (3x3) ....................................92  
Figure 47. STM8S003x value line ordering information scheme ...........................................................95  
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