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    STM32F103RCY7XXX 参数 Datasheet PDF下载

    STM32F103RCY7XXX图片预览
    型号： STM32F103RCY7XXX
    PDF下载： 下载PDF文件 查看货源
    内容描述： 高密度高性能线的基于ARM的32位MCU，具有256至512KB闪存， USB ， CAN ，11个定时器， 3的ADC ，13个通信接口 [High-density performance line ARM-based 32-bit MCU with 256 to 512KB Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces]
    分类和应用： 闪存通信
    文件页数/大小： 123 页 / 1691 K
    品牌： STMICROELECTRONICS [ STMICROELECTRONICS ]
     浏览型号STM32F103RCY7XXX的Datasheet PDF文件第115页浏览型号STM32F103RCY7XXX的Datasheet PDF文件第116页浏览型号STM32F103RCY7XXX的Datasheet PDF文件第117页浏览型号STM32F103RCY7XXX的Datasheet PDF文件第118页浏览型号STM32F103RCY7XXX的Datasheet PDF文件第119页浏览型号STM32F103RCY7XXX的Datasheet PDF文件第120页浏览型号STM32F103RCY7XXX的Datasheet PDF文件第122页浏览型号STM32F103RCY7XXX的Datasheet PDF文件第123页  
    STM32F103xC, STM32F103xD, STM32F103xE
    Table 72.
    Date
    Revision history
    Document revision history
    Revision
    Changes
    I/O information clarified
    on page 1. Figure 4: STM32F103xC and
    STM32F103xE performance line BGA100 ballout
    corrected.
    I/O information clarified
    on page 1.
    In
    Table 5: High-density STM32F103xx pin definitions:
    – I/O level of pins PF11, PF12, PF13, PF14, PF15, G0, G1 and G15
    updated
    – PB4, PB13, PB14, PB15, PB3/TRACESWO moved from Default
    column to Remap column
    PG14 pin description modified in
    Table 6: FSMC pin definition.
    Figure 9: Memory map on page 38
    modified.
    Note modified in
    Table 14: Maximum current consumption in Run mode,
    code with data processing running from Flash
    and
    Table 16: Maximum
    current consumption in Sleep mode, code running from Flash or RAM.
    Figure 17, Figure 18
    and
    Figure 19
    show typical curves (titles
    changed).
    Table 21: High-speed external user clock characteristics
    and
    Table 22:
    Low-speed external user clock characteristics
    modified. ACC
    HSI
    max
    values modified in
    Table 25: HSI oscillator characteristics.
    FSMC configuration modified for
    Asynchronous waveforms and timings.
    Notes modified below
    Figure 24: Asynchronous non-multiplexed
    SRAM/PSRAM/NOR read waveforms
    and
    Figure 25: Asynchronous
    non-multiplexed SRAM/PSRAM/NOR write waveforms.
    t
    w(NADV)
    values modified in
    Table 31: Asynchronous non-multiplexed
    SRAM/PSRAM/NOR read timings
    and
    Table 34: Asynchronous
    multiplexed PSRAM/NOR write timings.
    t
    h(Data_NWE)
    modified in
    Table 32: Asynchronous non-multiplexed SRAM/PSRAM/NOR write
    timings
    In
    Table 36: Synchronous multiplexed PSRAM write timings
    and
    Table 38: Synchronous non-multiplexed PSRAM write timings:
    – t
    v(Data-CLK)
    renamed as t
    d(CLKL-Data)
    – t
    d(CLKL-Data)
    min value removed and max value added
    – t
    h(CLKL-DV)
    / t
    h(CLKL-ADV)
    removed
    Figure 28: Synchronous multiplexed NOR/PSRAM read timings,
    Figure 29: Synchronous multiplexed PSRAM write timings
    and
    Figure 31: Synchronous non-multiplexed PSRAM write timings
    modified.
    Figure 48: I2S slave timing diagram (Philips protocol)(1)
    and
    Figure 49:
    I2S master timing diagram (Philips protocol)(1)
    modified.
    WLCSP64 package added (see
    Figure 8: STM32F103xC and
    STM32F103xE performance line WLCSP64 ballout, ball side, Table 5:
    High-density STM32F103xx pin definitions, Figure 61: WLCSP, 64-ball
    4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package
    outline
    and
    Table 66: WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm
    pitch, wafer-level chip-scale package mechanical data).
    Small text changes.
    30-Mar-2009
    5
    Doc ID 14611 Rev 7
    121/123

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