Electrical characteristics
STM32F103xC, STM32F103xD, STM32F103xE
Figure 24. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
t
w(NE)
FSMC_NE
t
v(NOE_NE)
t
w(NOE)
t
h(NE_NOE)
FSMC_NOE
FSMC_NWE
t
v(A_NE)
FSMC_A[25:0]
Address
t
h(A_NOE)
t
v(BL_NE)
FSMC_NBL[1:0]
t
h(BL_NOE)
t
h(Data_NE)
t
su(Data_NOE)
t
su(Data_NE)
t
h(Data_NOE)
FSMC_D[15:0]
t
v(NADV_NE)
t
w(NADV)
Data
FSMC_NADV
(1)
ai14991B
1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.
Table 31.
Symbol
t
w(NE)
t
v(NOE_NE)
t
w(NOE)
t
h(NE_NOE)
t
v(A_NE)
t
h(A_NOE)
t
v(BL_NE)
t
h(BL_NOE)
t
su(Data_NE)
t
h(Data_NOE)
t
h(Data_NE)
t
v(NADV_NE)
t
w(NADV)
1. C
L
= 15 pF.
Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings
(1) (2)
Parameter
FSMC_NE low time
FSMC_NEx low to FSMC_NOE low
FSMC_NOE low time
Min
5T
HCLK
– 1.5
0.5
5T
HCLK
– 1.5
Max
5T
HCLK
+ 2
1.5
5T
HCLK
+ 1.5
7
0.1
0
0
2T
HCLK
+ 25
2T
HCLK
+ 25
0
0
5
T
HCLK
+ 1.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
FSMC_NOE high to FSMC_NE high hold time –1.5
FSMC_NEx low to FSMC_A valid
Address hold time after FSMC_NOE high
FSMC_NEx low to FSMC_BL valid
FSMC_BL hold time after FSMC_NOE high
Data to FSMC_NEx high setup time
t
su(Data_NOE)
Data to FSMC_NOEx high setup time
Data hold time after FSMC_NOE high
Data hold time after FSMC_NEx high
FSMC_NEx low to FSMC_NADV low
FSMC_NADV low time
2. Based on characterization, not tested in production.
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Doc ID 14611 Rev 7