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STM32F103R4T7TR 参数 Datasheet PDF下载

STM32F103R4T7TR图片预览
型号: STM32F103R4T7TR
PDF下载: 下载PDF文件 查看货源
内容描述: 基于ARM的低密度高性能线的32位MCU,具有16或32 KB闪存, USB , CAN ,6个定时器, 2的ADC ,6个通信接口 [Low-density performance line, ARM-based 32-bit MCU with 16 or 32 KB Flash, USB, CAN, 6 timers, 2 ADCs, 6 communication interfaces]
分类和应用: 闪存微控制器和处理器外围集成电路通信时钟
文件页数/大小: 80 页 / 1067 K
品牌: STMICROELECTRONICS [ ST ]
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STM32F103x4, STM32F103x6  
Electrical characteristics  
5.3.11  
Absolute maximum ratings (electrical sensitivity)  
Based on three different tests (ESD, LU) using specific measurement methods, the device is  
stressed in order to determine its performance in terms of electrical sensitivity.  
Electrostatic discharge (ESD)  
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are  
applied to the pins of each sample according to each pin combination. The sample size  
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test  
conforms to the JESD22-A114/C101 standard.  
Table 32. ESD absolute maximum ratings  
Symbol  
Ratings  
Conditions  
Class Maximum value(1) Unit  
TA +25 °C  
conforming to  
JESD22-A114  
Electrostatic discharge  
voltage (human body model)  
VESD(HBM)  
2
2000  
500  
V
Electrostatic discharge  
VESD(CDM) voltage (charge device  
model)  
TA +25 °C  
conforming to  
JESD22-C101  
II  
1. Based on characterization results, not tested in production.  
Static latch-up  
Two complementary static tests are required on six parts to assess the latch-up  
performance:  
A supply overvoltage is applied to each power supply pin  
A current injection is applied to each input, output and configurable I/O pin  
These tests are compliant with EIA/JESD 78A IC latch-up standard.  
Table 33. Electrical sensitivities  
Symbol  
Parameter  
Conditions  
Class  
II level A  
LU  
Static latch-up class  
TA +105 °C conforming to JESD78A  
Doc ID 15060 Rev 3  
51/80  
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