Electrical characteristics
STM32F103xC, STM32F103xD, STM32F103xE
Figure 26. Asynchronous multiplexed PSRAM/NOR read waveforms
t
w(NE)
FSMC_NE
t
t
h(NE_NOE)
v(NOE_NE)
FSMC_NOE
t
w(NOE)
FSMC_NWE
t
tv(A_NE)
h(A_NOE)
FSMC_A[25:16]
Address
tv(BL_NE)
t
h(BL_NOE)
FSMC_NBL[1:0]
NBL
t
h(Data_NE)
t
su(Data_NE)
t
t
t
h(Data_NOE)
v(A_NE)
su(Data_NOE)
Address
Data
FSMC_AD[15:0]
FSMC_NADV
t
th(AD_NADV)
v(NADV_NE)
t
w(NADV)
ai14892b
(1)(2)
Table 33. Asynchronous multiplexed PSRAM/NOR read timings
Symbol
tw(NE)
tv(NOE_NE)
tw(NOE)
th(NE_NOE)
tv(A_NE)
Parameter
FSMC_NE low time
Min
Max
7THCLK + 2
Unit
ns
7THCLK – 2
FSMC_NEx low to FSMC_NOE low
FSMC_NOE low time
3THCLK – 0.5 3THCLK + 1.5 ns
4THCLK – 1
4THCLK + 2
ns
ns
ns
ns
ns
FSMC_NOE high to FSMC_NE high hold time –1
FSMC_NEx low to FSMC_A valid
0
tv(NADV_NE) FSMC_NEx low to FSMC_NADV low
3
5
tw(NADV)
FSMC_NADV low time
THCLK –1.5
THCLK + 1.5
FSMC_AD (address) valid hold time after
FSMC_NADV high
th(AD_NADV)
THCLK
ns
th(A_NOE)
th(BL_NOE)
tv(BL_NE)
Address hold time after FSMC_NOE high
FSMC_BL hold time after FSMC_NOE high
FSMC_NEx low to FSMC_BL valid
THCLK
0
ns
ns
ns
ns
ns
ns
ns
0
tsu(Data_NE) Data to FSMC_NEx high setup time
tsu(Data_NOE) Data to FSMC_NOE high setup time
2THCLK + 24
2THCLK + 25
th(Data_NE)
Data hold time after FSMC_NEx high
0
0
th(Data_NOE) Data hold time after FSMC_NOE high
1. CL = 15 pF.
2. Based on characterization, not tested in production.
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Doc ID 14611 Rev 7
STMICROELECTRONICS [ ST ]
