Electrical characteristics
Table 62.
Symbol
STM32F103xC, STM32F103xD, STM32F103xE
DAC characteristics (continued)
Parameter
Offset error
(difference between
measured value at Code
(0x800) and the ideal value =
V
REF+
/2)
Min
Typ
±10
±3
±12
±0.5
Max
Unit
mV
LSB
LSB
%
Comments
Given for the DAC in 12-bit
configuration
Given for the DAC in 10-bit at V
REF+
= 3.6 V
Given for the DAC in 12-bit at V
REF+
= 3.6 V
Given for the DAC in 12bit
configuration
Offset
(2)
Gain
error
(2)
Gain error
Settling time (full scale: for a
10-bit input code transition
between the lowest and the
highest input codes when
DAC_OUT reaches final
value ±1LSB
Max frequency for a correct
DAC_OUT change when
small variation in the input
code (from code i to i+1LSB)
Wakeup time from off state
(Setting the ENx bit in the
DAC Control register)
Power supply rejection ratio
(to V
DDA
) (static DC
measurement
6.5
t
SETTLING(2)
3
4
µs
C
LOAD
50 pF, R
LOAD
5 k
Update
rate
(2)
1
MS/s C
LOAD
50 pF, R
LOAD
5 k
C
LOAD
50 pF, R
LOAD
5 k
input code between lowest and
highest possible ones.
No R
LOAD
, C
LOAD
= 50 pF
t
WAKEUP(2)
10
µs
PSRR+
(1)
–67
–40
dB
1. Guaranteed by design, not tested in production.
2. Guaranteed by characterization, not tested in production.
Figure 57. 12-bit buffered /non-buffered DAC
Buffered/Non-buffered DAC
Buffer(1)
R
LOAD
12-bit
digital to
analog
converter
DACx_OUT
C
LOAD
ai17157
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
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Doc ID 14611 Rev 7
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