STM32F103xC, STM32F103xD, STM32F103xE
Electrical characteristics
Figure 31. Synchronous non-multiplexed PSRAM write timings
BUSTURN = 0
t
t
w(CLK)
w(CLK)
FSMC_CLK
t
t
d(CLKL-NExL)
d(CLKH-NExH)
Data latency = 1
d(CLKL-NADVH)
FSMC_NEx
t
t
d(CLKL-NADVL)
FSMC_NADV
FSMC_A[25:0]
FSMC_NWE
t
t
t
d(CLKH-AIV)
d(CLKL-AV)
t
d(CLKL-NWEL)
t
d(CLKH-NWEH)
t
d(CLKL-Data)
d(CLKL-Data)
FSMC_D[15:0]
D1
D2
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
FSMC_NBL
t
t
d(CLKL-NBLH)
su(NWAITV-CLKH)
t
h(CLKH-NWAITV)
ai14993e
(1)(2)
Table 38. Synchronous non-multiplexed PSRAM write timings
Symbol Parameter
tw(CLK)
Min
27.7
Max Unit
FSMC_CLK period
ns
td(CLKL-NExL)
td(CLKH-NExH)
td(CLKL-NADVL)
td(CLKL-NADVH)
td(CLKL-AV)
FSMC_CLK low to FSMC_NEx low (x = 0...2)
FSMC_CLK high to FSMC_NEx high (x = 0...2)
FSMC_CLK low to FSMC_NADV low
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
THCLK + 2
4
0
1
6
FSMC_CLK low to FSMC_NADV high
5
FSMC_CLK low to FSMC_Ax valid (x = 16...25)
FSMC_CLK high to FSMC_Ax invalid (x = 16...25)
FSMC_CLK low to FSMC_NWE low
td(CLKH-AIV)
TCK + 2
td(CLKL-NWEL)
td(CLKH-NWEH)
td(CLKL-Data)
FSMC_CLK high to FSMC_NWE high
THCLK + 1
FSMC_D[15:0] valid data after FSMC_CLK low
tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high
th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high
7
2
1
td(CLKL-NBLH)
1. CL = 15 pF.
FSMC_CLK low to FSMC_NBL high
2. Based on characterization, not tested in production.
Doc ID 14611 Rev 7
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