STM32F103xC, STM32F103xD, STM32F103xE
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram . . . 12
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
STM32F103xC and STM32F103xE performance line BGA144 ballout . . . . . . . . . . . . . . . 24
STM32F103xC and STM32F103xE performance line BGA100 ballout . . . . . . . . . . . . . . . 25
STM32F103xC and STM32F103xE performance line LQFP144 pinout. . . . . . . . . . . . . . . 26
STM32F103xC and STM32F103xE performance line LQFP100 pinout. . . . . . . . . . . . . . . 27
STM32F103xC and STM32F103xE performance line
LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
STM32F103xC and STM32F103xE performance line
WLCSP64 ballout, ball side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 8.
Figure 9.
Figure 10. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 11. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 12. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 13. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 14. Typical current consumption in Run mode versus frequency (at 3.6 V) -
code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 46
Figure 15. Typical current consumption in Run mode versus frequency (at 3.6 V) -
code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 46
Figure 16. Typical current consumption on V
with RTC on vs. temperature at different V
BAT
BAT
values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 17. Typical current consumption in Stop mode with regulator in run mode
versus temperature at different V values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
DD
Figure 18. Typical current consumption in Stop mode with regulator in low-power
mode versus temperature at different V values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
DD
Figure 19. Typical current consumption in Standby mode versus temperature at
different V values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
DD
Figure 20. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 21. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 22. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 23. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 24. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . . 62
Figure 25. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . . 63
Figure 26. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 27. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 28. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 29. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 30. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 31. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 32. PC Card/CompactFlash controller waveforms for common memory read access . . . . . . . 72
Figure 33. PC Card/CompactFlash controller waveforms for common memory write access. . . . . . . 73
Figure 34. PC Card/CompactFlash controller waveforms for attribute memory read
access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 35. PC Card/CompactFlash controller waveforms for attribute memory write
access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 36. PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . . 75
Figure 37. PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . . 76
Figure 38. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Doc ID 14611 Rev 7
7/123
STMICROELECTRONICS [ ST ]
