STM32F103xC, STM32F103xD, STM32F103xE
Electrical characteristics
2
Table 53. I S characteristics
Symbol
Parameter
Conditions
Slave mode
Min
Max
Unit
I2S slave input clock duty
cycle
DuCy(SCK)
30
70
%
Master mode (data: 16 bits,
Audio frequency = 48 kHz)
1.522
0
1.525
6.5
8
fCK
1/tc(CK)
I2S clock frequency
MHz
ns
Slave mode
tr(CK)
tf(CK)
I2S clock rise and fall time
WS valid time
Capacitive load CL = 50 pF
Master mode
(1)
tv(WS)
3
2
I2S2
I2S3
(1)
th(WS)
WS hold time
Master mode
0
(1)
tsu(WS)
WS setup time
WS hold time
Slave mode
Slave mode
4
(1)
th(WS)
0
(1)
tw(CKH)
312.5
345
2
Master fPCLK= 16 MHz, audio
frequency = 48 kHz
CK high and low time
(1)
tw(CKL)
I2S2
Master receiver
I2S3
(1)
tsu(SD_MR)
Data input setup time
Data input setup time
Data input hold time
6.5
1.5
0
(1)
tsu(SD_SR)
Slave receiver
Master receiver
Slave receiver
(1)(2)
th(SD_MR)
th(SD_SR)
(1)(2)
0.5
Slave transmitter (after enable
edge)
(1)(2)
tv(SD_ST)
th(SD_ST)
tv(SD_MT)
th(SD_MT)
Data output valid time
Data output hold time
Data output valid time
Data output hold time
18
3
Slave transmitter (after enable
edge)
(1)
11
0
Master transmitter (after enable
edge)
(1)(2)
(1)
Master transmitter (after enable
edge)
1. Based on design simulation and/or characterization results, not tested in production.
2. Depends on fPCLK. For example, if fPCLK=8 MHz, then TPCLK = 1/fPLCLK =125 ns.
Doc ID 14611 Rev 7
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STMICROELECTRONICS [ ST ]
