STM32F103xC, STM32F103xD, STM32F103xE
Electrical characteristics
Figure 27. Asynchronous multiplexed PSRAM/NOR write waveforms
t
w(NE)
FSMC_NEx
FSMC_NOE
t
v(NWE_NE)
t
w(NWE)
t
h(NE_NWE)
FSMC_NWE
t
v(A_NE)
FSMC_A[25:16]
Address
t
h(A_NWE)
t
v(BL_NE)
FSMC_NBL[1:0]
t
v(A_NE)
NBL
t
h(BL_NWE)
t
v(Data_NADV)
Data
t
h(Data_NWE)
FSMC_AD[15:0]
Address
t
v(NADV_NE)
t
w(NADV)
t
h(AD_NADV)
FSMC_NADV
ai14891B
Table 34.
Symbol
t
w(NE)
t
v(NWE_NE)
t
w(NWE)
t
h(NE_NWE)
t
v(A_NE)
t
v(NADV_NE)
t
w(NADV)
t
h(AD_NADV)
t
h(A_NWE)
t
v(BL_NE)
t
h(BL_NWE)
Asynchronous multiplexed PSRAM/NOR write timings
(1)(2)
Parameter
FSMC_NE low time
FSMC_NEx low to FSMC_NWE low
FSMC_NWE low time
FSMC_NWE high to FSMC_NE high hold time
FSMC_NEx low to FSMC_A valid
FSMC_NEx low to FSMC_NADV low
FSMC_NADV low time
FSMC_AD (address) valid hold time after
FSMC_NADV high
Address hold time after FSMC_NWE high
FSMC_NEx low to FSMC_BL valid
FSMC_BL hold time after FSMC_NWE high
T
HCLK
– 1.5
T
HCLK
+ 1.5
T
HCLK
– 5
3
T
HCLK
– 1
T
HCLK
– 3
4T
HCLK
1.6
Min
5T
HCLK
– 1
2T
HCLK
2T
HCLK
– 1
T
HCLK
– 1
7
5
T
HCLK
+ 1
Max
5T
HCLK
+ 2
2T
HCLK
+ 1
2T
HCLK
+ 2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
v(Data_NADV)
FSMC_NADV high to Data valid
t
h(Data_NWE)
1. C
L
= 15 pF.
2. Based on characterization, not tested in production.
Data hold time after FSMC_NWE high
Doc ID 14611 Rev 7
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