STM32F103xC, STM32F103xD, STM32F103xE
Electrical characteristics
(1)(2)
Table 39. Switching characteristics for PC Card/CF read and write cycles
(continued)
Max
Symbol
tw(NIOWR)
tv(NIOWR-D)
th(NIOWR-D)
Parameter
FSMC_NIOWR low width
Min
Unit
8THCLK + 3
ns
ns
ns
FSMC_NIOWR low to FSMC_D[15:0] valid
FSMC_NIOWR high to FSMC_D[15:0] invalid
5THCLK +1
11THCLK
td(NCE4_1-NIOWR) FSMC_NCE4_1 low to FSMC_NIOWR valid
5THCLK+3ns ns
ns
th(NCEx-NIOWR) FSMC_NCEx high to FSMC_NIOWR invalid
5THCLK – 5
th(NCE4_1-NIOWR) FSMC_NCE4_1 high to FSMC_NIOWR invalid
td(NIORD-NCEx) FSMC_NCEx low to FSMC_NIORD valid FSMC_NCE4_1
5THCLK + 2.5 ns
ns
td(NIORD-NCE4_1) low to FSMC_NIORD valid
th(NCEx-NIORD)
FSMC_NCEx high to FSMC_NIORD invalid
5THCLK – 5
th(NCE4_1-NIORD) FSMC_NCE4_1 high to FSMC_NIORD invalid
tsu(D-NIORD)
td(NIORD-D)
tw(NIORD)
FSMC_D[15:0] valid before FSMC_NIORD high
FSMC_D[15:0] valid after FSMC_NIORD high
FSMC_NIORD low width
4.5
ns
ns
ns
9
8THCLK + 2
1. CL = 15 pF.
2. Based on characterization, not tested in production.
NAND controller waveforms and timings
Figure 38 through Figure 41 represent synchronous waveforms and Table 40 provides the
corresponding timings. The results shown in this table are obtained with the following FSMC
configuration:
●
●
●
●
●
●
●
●
●
●
●
●
●
●
COM.FSMC_SetupTime = 0x01;
COM.FSMC_WaitSetupTime = 0x03;
COM.FSMC_HoldSetupTime = 0x02;
COM.FSMC_HiZSetupTime = 0x01;
ATT.FSMC_SetupTime = 0x01;
ATT.FSMC_WaitSetupTime = 0x03;
ATT.FSMC_HoldSetupTime = 0x02;
ATT.FSMC_HiZSetupTime = 0x01;
Bank = FSMC_Bank_NAND;
MemoryDataWidth = FSMC_MemoryDataWidth_16b;
ECC = FSMC_ECC_Enable;
ECCPageSize = FSMC_ECCPageSize_512Bytes;
TCLRSetupTime = 0;
TARSetupTime = 0;
Doc ID 14611 Rev 7
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STMICROELECTRONICS [ ST ]
