STM32F103xC, STM32F103xD, STM32F103xE
Figure 2.
Clock tree
USB
Prescaler
/1, 1.5
Description
48 MHz
USBCLK
to USB interface
I2S3CLK
Peripheral clock
enable
to I2S3
I2S2CLK
to I2S2
SDIOCLK
FSMCCLK
to SDIO
to FSMC
8 MHz
HSI RC
HSI
Peripheral clock
enable
Peripheral clock
enable
/2
Peripheral clock
enable
72 MHz max
Clock
Enable (4 bits)
HCLK
to AHB bus, core,
memory and DMA
to Cortex System timer
FCLK Cortex
free running clock
PCLK1
to APB1
peripherals
Peripheral Clock
Enable (20 bits)
PLLSRC
PLLMUL
..., x16
x2, x3, x4
PLL
HSI
PLLCLK
HSE
SW
SYSCLK
/8
AHB
Prescaler
72 MHz
/1, 2..512
max
APB1
Prescaler
/1, 2, 4, 8, 16
36 MHz max
CSS
TIM2,3,4,5,6,7
If (APB1 prescaler =1) x1
else x2
to TIM2,3,4,5,6 and 7
TIMXCLK
Peripheral Clock
Enable (6 bits)
PLLXTPRE
OSC_OUT
OSC_IN
4-16 MHz
HSE OSC
/2
APB2
Prescaler
/1, 2, 4, 8, 16
72 MHz max
Peripheral Clock
Enable (15 bits)
PCLK2
peripherals to APB2
TIM1 & 8 timers
If (APB2 prescaler =1) x1
else x2
to TIM1 and TIM8
TIMxCLK
Peripheral Clock
Enable (2 bit)
to ADC1, 2 or 3
/128
OSC32_IN
OSC32_OUT
LSE OSC
32.768 kHz
LSE
to RTC
RTCCLK
RTCSEL[1:0]
ADC
Prescaler
/2, 4, 6, 8
/2
ADCCLK
HCLK/2
LSI RC
40 kHz
LSI
to Independent Watchdog (IWDG)
To SDIO AHB interface
Peripheral clock
enable
IWDGCLK
Main
Clock Output
/2
PLLCLK
HSI
HSE
SYSCLK
Legend:
HSE = High Speed External clock signal
HSI = High Speed Internal clock signal
LSI = Low Speed Internal clock signal
LSE = Low Speed External clock signal
ai14752b
MCO
MCO
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
64 MHz.
2. For the USB function to be available, both HSE and PLL must be enabled, with the CPU running at either
48 MHz or 72 MHz.
3. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz, 28 MHz or 56 MHz.
Doc ID 14611 Rev 7
13/123
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