STM32F103xC, STM32F103xD, STM32F103xE
Figure 54. Typical connection diagram using the ADC
VDD
VT
0.6 V
AINx
Cparasitic
VT
0.6 V
IL±1 µA
Electrical characteristics
RAIN(1)
STM32F103xx
Sample and hold ADC
converter
RADC(1)
12-bit
converter
CADC(1)
VAIN
ai14150c
1. Refer to
for the values of R
AIN
, R
ADC
and C
ADC
.
2. C
parasitic
represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high C
parasitic
value will downgrade conversion accuracy. To remedy
this, f
ADC
should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in
or
depending on whether V
REF+
is connected to V
DDA
or not. The 10 nF capacitors should be
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 55. Power supply and reference decoupling (V
REF+
not connected to
V
DDA
)
STM32F103xx
V
REF+
(see note 1)
1 µF // 10 nF
V
DDA
1 µF // 10 nF
V
SSA
/V
REF–
(see note 1)
ai14388b
1. V
REF+
and V
REF–
inputs are available only on 100-pin packages.
Doc ID 14611 Rev 7
101/123
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