STM32F103x4, STM32F103x6
Pinouts and pin description
Alternate functions(4)
Table 5.
Pins
Low-density STM32F103xx pin definitions (continued)
Main
Pin name
function(3)
(after reset)
Default
Remap
5
6
5
C1
D1
2
3
-
PD0
PD1
PD2
I/O FT OSC_IN(9)
I/O FT OSC_OUT(9)
6
54 B5
I/O FT
PD2
TIM3_ETR
TIM2_CH2 / PB3/
TRACESWO
SPI1_SCK
39 55 A5 30
PB3
I/O FT
JTDO
TIM3_CH1 /PB4
SPI1_MISO
40 56 A4 31
41 57 C4 32
PB4
PB5
I/O FT
I/O
NJTRST
PB5
TIM3_CH2 /
SPI1_MOSI
I2C1_SMBA
42 58 D3 33
43 59 C3 34
44 60 B4 35
PB6
PB7
I/O FT
I/O FT
I
PB6
PB7
I2C1_SCL(8)
I2C1_SDA(8)
/
USART1_TX
USART1_RX
BOOT0
BOOT0
I2C1_SCL
/CAN_RX
45 61 B3
46 62 A3
-
-
PB8
PB9
I/O FT
I/O FT
PB8
PB9
I2C1_SDA /
CAN_TX
47 63 D4 36
48 64 E4
VSS_3
VDD_3
S
S
VSS_3
VDD_3
1
1. I = input, O = output, S = supply.
2. FT = 5 V tolerant.
3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower
number of peripheral that is included. For example, if a device has only one SPI and two USARTs, they will be called SPI1
and USART1 & USART2, respectively. Refer to Table 2 on page 9.
4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should
be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum
load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).
6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even
after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the
Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the
STMicroelectronics website: www.st.com.
7. Unlike in the LQFP64 package, there is no PC3 in the TFBGA64 package. The VREF+ functionality is provided instead.
8. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual,
available from the STMicroelectronics website: www.st.com.
9. The pins number 2 and 3 in the VFQFPN36 package, 5 and 6 in the LQFP48 and LQFP64 packages and C1 and C2 in the
TFBGA64 package are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be
remapped by software on these pins. For more details, refer to the Alternate function I/O and debug configuration section
in the STM32F10xxx reference manual.
Doc ID 15060 Rev 3
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