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    STM32F103C8U6XXX 参数 Datasheet PDF下载

    STM32F103C8U6XXX图片预览
    型号： STM32F103C8U6XXX
    PDF下载： 下载PDF文件 查看货源
    内容描述： 中密度高性能线的基于ARM的32位MCU，具有64或128 KB的闪存， USB ， CAN ，7个定时器， 2的ADC ，9个通信接口 [Medium-density performance line ARM-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 communication interfaces]
    分类和应用： 闪存通信
    文件页数/大小： 92 页 / 1212 K
    品牌： STMICROELECTRONICS [ STMICROELECTRONICS ]
     浏览型号STM32F103C8U6XXX的Datasheet PDF文件第83页浏览型号STM32F103C8U6XXX的Datasheet PDF文件第84页浏览型号STM32F103C8U6XXX的Datasheet PDF文件第85页浏览型号STM32F103C8U6XXX的Datasheet PDF文件第86页浏览型号STM32F103C8U6XXX的Datasheet PDF文件第88页浏览型号STM32F103C8U6XXX的Datasheet PDF文件第89页浏览型号STM32F103C8U6XXX的Datasheet PDF文件第90页浏览型号STM32F103C8U6XXX的Datasheet PDF文件第91页  
    STM32F103x8, STM32F103xB
    Table 58.
    Date
    Revision history
    Document revision history (continued)
    Revision
    Changes
    STM32F103CBT6, STM32F103T6 and STM32F103T8 root part
    numbers added (see
    Table 2: STM32F103xx medium-density device
    features and peripheral counts)
    VFQFPN36 package added (see
    Section 6: Package characteristics).
    All packages are ECOPACK® compliant. Package mechanical data
    inch values are calculated from mm and rounded to 4 decimal digits
    (see
    Section 6: Package characteristics).
    Table 5: Medium-density STM32F103xx pin definitions
    updated and
    clarified.
    Table 26: Low-power mode wakeup timings
    updated.
    T
    A
    min corrected in
    Table 12: Embedded internal reference voltage.
    Note 2
    added below
    Table 22: HSE 4-16 MHz oscillator characteristics.
    V
    ESD(CDM)
    value added to
    Table 32: ESD absolute maximum ratings.
    Note 3
    added and V
    OH
    parameter description modified in
    Table 35:
    Output voltage characteristics.
    Note 1
    modified under
    Table 36: I/O AC characteristics.
    Equation 1
    and
    Table 46: RAIN max for fADC = 14 MHz
    added to
    Section 5.3.17: 12-bit ADC characteristics.
    V
    AIN
    , t
    S
    max, t
    CONV
    , V
    REF+
    min and t
    lat
    max modified, notes modified
    and t
    latr
    added in
    Table 45: ADC characteristics.
    Figure 31: ADC accuracy characteristics
    updated.
    Note 1
    modified
    below
    Figure 32: Typical connection diagram using the ADC.
    Electrostatic discharge (ESD) on page 56
    modified.
    Number of TIM4 channels modified in
    Figure 1: STM32F103xx
    performance line block diagram.
    Maximum current consumption
    Table 13, Table 14
    and
    Table 15
    updated. V
    hys
    modified in
    Table 34: I/O static characteristics.
    Table 48: ADC accuracy
    updated. t
    VDD
    modified in
    Table 10: Operating
    conditions at power-up / power-down.
    V
    FESD
    value added in
    Table 30:
    EMS characteristics.
    Values corrected, note 2 modified and note 3 removed in
    Table 26:
    Low-power mode wakeup timings.
    Table 16: Typical and maximum current consumptions in Stop and
    Standby modes:
    Typical values added for V
    DD
    /V
    BAT
    = 2.4 V,
    Note 2
    modified,
    Note 2
    added.
    Table 21: Typical current consumption in Standby mode
    added.
    On-chip
    peripheral current consumption on page 47
    added.
    ACC
    HSI
    values updated in
    Table 24: HSI oscillator characteristics.
    V
    prog
    added to
    Table 28: Flash memory characteristics.
    Upper option byte address modified in
    Figure 9: Memory map.
    Typical f
    LSI
    value added in
    Table 25: LSI oscillator characteristics
    and
    internal RC value corrected from 32 to 40 kHz in entire document.
    T
    S_temp
    added to
    Table 49: TS characteristics.
    N
    END
    modified in
    Table 29: Flash memory endurance and data retention.
    T
    S_vrefint
    added to
    Table 12: Embedded internal reference voltage.
    Handling of unused pins specified in
    General input/output
    characteristics on page 57.
    All I/Os are CMOS and TTL compliant.
    Figure 33: Power supply and reference decoupling (VREF+ not
    connected to VDDA)
    modified.
    t
    JITTER
    and f
    VCO
    removed from
    Table 27: PLL characteristics.
    Appendix A: Important notes on page 81
    added.
    Added
    Figure 14, Figure 15, Figure 17
    and
    Figure 19.
    18-Oct-2007
    3
    Doc ID 13587 Rev 11
    87/92

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