STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB
Pinouts and pin description
Alternate functions(3)(4)
Table 4.
Pins
STM32F100xx pin definitions (continued)
Main
Pin name
function(3)
Default
Remap
(after reset)
PB4 / TIM3_CH1
SPI1_MISO
90 56 A4 40
91 57 C4 41
92 58 D3 42
PB4
PB5
PB6
I/O FT
I/O
NJTRST
PB5
TIM3_CH2 /
SPI1_MOSI
I2C1_SMBA / TIM16_BKIN
I2C1_SCL(12)/ TIM4_CH1(10)(12)
TIM16_CH1N
I/O FT
PB6
USART1_TX
USART1_RX
I2C1_SDA(12)/ TIM17_CH1N
TIM4_CH2(10)(12)
93 59 C3 43
94 60 B4 44
95 61 B3 45
PB7
BOOT0
PB8
I/O FT
I
PB7
BOOT0
PB8
TIM4_CH3(10)(12)
TIM16_CH1(12) / CEC(12)
/
I/O FT
I2C1_SCL
I2C1_SDA
TIM4_CH4(10)(12)
TIM17_CH1(12)
/
96 62 A3 46
PB9
I/O FT
PB9
97
98
-
-
-
-
-
-
PE0
PE1
I/O FT
PE0
PE1
TIM4_ETR(10)
I/O FT
99 63 D4 47
100 64 E4 48
VSS_3
VDD_3
S
S
VSS_3
VDD_3
1. I = input, O = output, S = supply, HiZ= high impedance.
2. FT= 5 V tolerant.
3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower
number of peripherals that is included. For example, if a device has only one SPI, two USARTs and two timers, they will be
called SPI1, USART1 & USART2 and TIM2 & TIM 3, respectively. Refer to Table 2 on page 11.
4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should
be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
5. PC13, PC14 and PC15 are supplied through the power switch and since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 in output mode is restricted: the speed should not exceed 2 MHz with a maximum
load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).
6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even
after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the
Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the
STMicroelectronics website: www.st.com.
7. Unlike in the LQFP64 package, there is no PC3 in the TFBGA64 package. The VREF+ functionality is provided instead.
8. I2C2 is not present on low-density value line devices.
9. SPI2 is not present on low-density value line devices.
10. TIM4 is not present on low-density value line devices.
11. The pins number 2 and 3 in the VFQFPN36 package, 5 and 6 in the LQFP48 and LQFP64 packages and C1 and C2 in the
TFBGA64 package are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be
remapped by software on these pins. For more details, refer to the Alternate function I/O and debug configuration section in
the STM32F10xxx reference manual.
12. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available
from the STMicroelectronics website: www.st.com.
Doc ID 16455 Rev 2
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