Electrical characteristics
STM32F103xC, STM32F103xD, STM32F103xE
5.3.18
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 58 are derived from tests
performed under ambient temperature, f
frequency and V
supply voltage
PCLK2
DDA
conditions summarized in Table 10.
Note:
It is recommended to perform a calibration after each power-up.
Table 58. ADC characteristics
Symbol
Parameter
Power supply
Conditions
Min
Typ
Max
Unit
VDDA
2.4
2.4
3.6
V
V
VREF+
Positive reference voltage
VDDA
Current on the VREF input
pin
IVREF
fADC
160(1) 220(1)
µA
ADC clock frequency
Sampling rate
0.6
14
1
MHz
MHz
(2)
0.05
fS
f
ADC = 14 MHz
823
17
kHz
(2)
External trigger frequency
Conversion voltage range(3)
fTRIG
1/fADC
0 (VSSA or VREF-
tied to ground)
VAIN
VREF+
V
See Equation 1 and
Table 59 for details
(2)
RAIN
External input impedance
Sampling switch resistance
50
1
k
k
pF
(2)
RADC
Internal sample and hold
capacitor
(2)
8
CADC
fADC = 14 MHz
fADC = 14 MHz
fADC = 14 MHz
fADC = 14 MHz
5.9
83
µs
1/fADC
µs
(2)
Calibration time
tCAL
0.214
3(4)
Injection trigger conversion
latency
(2)
tlat
1/fADC
µs
0.143
2(4)
Regular trigger conversion
latency
(2)
tlatr
1/fADC
µs
0.107
1.5
0
17.1
239.5
(2)
Sampling time
Power-up time
tS
1/fADC
µs
(2)
tSTAB
0
1
fADC = 14 MHz
1
18
µs
Total conversion time
(including sampling time)
(2)
tCONV
14 to 252 (tS for sampling +12.5 for
successive approximation)
1/fADC
1. Based on characterization results, not tested in production.
2. Guaranteed by design, not tested in production.
3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package.
Refer to Section 3: Pinouts and pin descriptions for further details.
4. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 58.
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