Electrical characteristics
STM32F103xC, STM32F103xD, STM32F103xE
Figure 42. I/O AC characteristics definition
90%
50%
10%
EXT ERNAL
OUTPUT
ON 50pF
tr(I O)out
T
10%
50%
90%
tr(I O)out
Maximum frequency is achieved if (tr + tf)
2/3)T
and if the duty cycle is (45-55%)
when loaded by 50pF
ai14131
5.3.14
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R
PU
(see
Unless otherwise specified, the parameters given in
are derived from tests
performed under ambient temperature and V
DD
supply voltage conditions summarized in
Table 48.
Symbol
NRST pin characteristics
Parameter
Conditions
Min
–0.5
2
200
V
IN
�½
V
SS
30
40
50
100
300
Typ
Max
0.8
V
V
DD
+0.5
mV
k
ns
ns
Unit
V
IL(NRST)(1)
NRST Input low level voltage
V
IH(NRST)(1)
NRST Input high level voltage
V
hys(NRST)
R
PU
V
F(NRST)(1)
NRST Schmitt trigger voltage
hysteresis
Weak pull-up equivalent resistor
(2)
NRST Input filtered pulse
V
NF(NRST)(1)
NRST Input not filtered pulse
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
to the series resistance must be minimum
(~10% order)
.
Figure 43. Recommended NRST pin protection
VDD
NRST
(2)
RPU
Filter
0.1
µF
Internal Reset
External
reset circuit
(1)
STM32F10xxx
ai14132c
2. The reset network protects the device against parasitic resets.
3. The user must ensure that the level on the NRST pin can go below the V
IL(NRST)
max level specified in
Otherwise the reset will not be taken into account by the device.
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Doc ID 14611 Rev 7
STMICROELECTRONICS [ STMICROELECTRONICS ]
