Electrical characteristics
STM32F103xC, STM32F103xD, STM32F103xE
Figure 29. Synchronous multiplexed PSRAM write timings
BUSTURN = 0
t
t
w(CLK)
w(CLK)
FSMC_CLK
Data latency = 1
d(CLKL-NExL)
t
t
d(CLKH-NExH)
FSMC_NEx
t
t
d(CLKL-NADVL)
d(CLKL-NADVH)
FSMC_NADV
t
t
t
d(CLKH-AIV)
d(CLKL-AV)
FSMC_A[25:16]
FSMC_NWE
t
d(CLKL-NWEL)
d(CLKH-NWEH)
t
t
d(CLKL-ADIV)
t
d(CLKL-Data)
D1
t
d(CLKL-Data)
d(CLKL-ADV)
FSMC_AD[15:0]
AD[15:0]
D2
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
FSMC_NBL
t
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
t
d(CLKL-NBLH)
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Doc ID 14611 Rev 7