STM32F103x8, STM32F103xB
Table 5.
Pinouts and pin description
Medium-density STM32F103xx pin definitions (continued)
Pins
Alternate functions
(4)
I / O Level
(2)
LQFP48/VFQFPN48
VFQFPN36
LFBGA100
TFBGA64
LQFP100
LQFP64
Pin name
Main
function
(3)
(after reset)
Type
(1)
Default
Remap
C5
B5
A5
D5
B4
A4
D4
C4
E5
F5
41
42
43
44
45
46
-
-
47
48
C4
D3
C3
B4
B3
A3
-
-
D4
E4
57
58
59
60
61
62
-
-
63
64
91
92
93
94
95
96
97
98
99
100
32
33
34
35
-
-
-
-
36
1
PB5
PB6
PB7
BOOT0
PB8
PB9
PE0
PE1
V
SS_3
V
DD_3
I/O
I/O FT
I/O FT
I
I/O FT
I/O FT
I/O FT
I/O FT
S
S
PB5
PB6
PB7
BOOT0
PB8
PB9
PE0
PE1
V
SS_3
V
DD_3
I2C1_SMBAl
I2C1_SCL
(8)
/
TIM4_CH1
(8)
I2C1_SDA
(8)
/
TIM4_CH2
(8)
TIM3_CH2 /
SPI1_MOSI
USART1_TX
USART1_RX
TIM4_CH3
(8)
TIM4_CH4
(8)
TIM4_ETR
I2C1_SCL /
CANRX
I2C1_SDA/
CANTX
1. I = input, O = output, S = supply.
2. FT = 5 V tolerant.
3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower
number of peripheral that is included. For example, if a device has only one SPI and two USARTs, they will be called SPI1
and USART1 & USART2, respectively. Refer to
4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should
be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum
load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).
6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even
after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the
Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the
STMicroelectronics website: www.st.com.
7. Unlike in the LQFP64 package, there is no PC3 in the TFBGA64 package. The V
REF+
functionality is provided instead.
8. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available
from the STMicroelectronics website: www.st.com.
9. The pins number 2 and 3 in the VFQFPN36 package, 5 and 6 in the LQFP48 and LQFP64 packages, and C1 and C2 in the
TFBGA64 package are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be
remapped by software on these pins. For the LQFP100 package, PD0 and PD1 are available by default, so there is no
need for remapping. For more details, refer to the Alternate function I/O and debug configuration section in the
STM32F10xxx reference manual.
The use of PD0 and PD1 in output mode is limited as they can only be used at 50 MHz in output mode.
Doc ID 13587 Rev 12
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