Functional overview
STM32F302xx/STM32F303xx
3.4
3.5
3.6
Embedded SRAM
STM32F302xx/STM32F303xx devices feature up to 48 Kbytes of embedded SRAM with
hardware parity check. The memory can be accessed in read/write at CPU clock speed with
0 wait states, allowing the CPU to achieve 90 Dhrystone Mips at 72 MHz (when running
code from CCM, core coupled memory).
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8 Kbytes of SRAM mapped on the instruction bus (Core Coupled Memory (CCM)),
used to execute critical routines or to access data (parity check on all of CCM RAM).
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40 Kbytes of SRAM mapped on the data bus (parity check on first 16 Kbytes of SRAM).
Boot modes
At startup, Boot0 pin and Boot1 option bit are used to select one of three boot options:
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Boot from user Flash
Boot from system memory
Boot from embedded SRAM
The boot loader is located in system memory. It is used to reprogram the Flash memory by
using USART1 (PA9/PA10), USART2 (PD5/PD6) or USB (PA11/PA12) through DFU (device
firmware upgrade) .
Cyclic redundancy check (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at
linktime and stored at a given memory location.
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Doc ID 023353 Rev 5
STMICROELECTRONICS [ ST ]
