STM32F103xC, STM32F103xD, STM32F103xE
Electrical characteristics
5.3.2
Operating conditions at power-up / power-down
The parameters given in Table 11 are derived from tests performed under the ambient
temperature condition summarized in Table 10.
Table 11. Operating conditions at power-up / power-down
Symbol
Parameter
Conditions
Min
Max
∞
Unit
VDD rise time rate
0
tVDD
µs/V
V
DD fall time rate
20
∞
5.3.3
Embedded reset and power control block characteristics
The parameters given in Table 12 are derived from tests performed under ambient
temperature and V supply voltage conditions summarized in Table 10.
DD
Table 12. Embedded reset and power control block characteristics
Symbol
Parameter
Conditions
Min
Typ Max Unit
PLS[2:0]=000 (rising edge)
PLS[2:0]=000 (falling edge)
PLS[2:0]=001 (rising edge)
PLS[2:0]=001 (falling edge)
PLS[2:0]=010 (rising edge)
PLS[2:0]=010 (falling edge)
PLS[2:0]=011 (rising edge)
PLS[2:0]=011 (falling edge)
PLS[2:0]=100 (rising edge)
PLS[2:0]=100 (falling edge)
PLS[2:0]=101 (rising edge)
PLS[2:0]=101 (falling edge)
PLS[2:0]=110 (rising edge)
PLS[2:0]=110 (falling edge)
PLS[2:0]=111 (rising edge)
PLS[2:0]=111 (falling edge)
2.1 2.18 2.26
2.08 2.16
V
V
2
2.19 2.28 2.37
2.09 2.18 2.27
2.28 2.38 2.48
2.18 2.28 2.38
2.38 2.48 2.58
2.28 2.38 2.48
2.47 2.58 2.69
2.37 2.48 2.59
2.57 2.68 2.79
2.47 2.58 2.69
2.66 2.78 2.9
2.56 2.68 2.8
V
V
V
V
V
V
Programmable voltage
detector level selection
VPVD
V
V
V
V
V
V
2.76 2.88
3
V
2.66 2.78 2.9
100
V
(2)
VPVDhyst
PVD hysteresis
mV
V
1.8(1)
Falling edge
Rising edge
1.88 1.96
Power on/power down
reset threshold
VPOR/PDR
1.84 1.92 2.0
40
V
(2)
VPDRhyst
PDR hysteresis
mV
mS
(2)
TRSTTEMPO
Reset temporization
1
2.5
4.5
1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
2. Guaranteed by design, not tested in production.
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STMICROELECTRONICS [ ST ]
