Electrical characteristics
STM32F103xC, STM32F103xD, STM32F103xE
Figure 58. Typical connection diagram using the ADC
V
DD
STM32F103xx
Sample and hold ADC
converter
V
0.6 V
T
(1)
(1)
AIN
R
R
ADC
AINx
12-bit
converter
I
1 µA
L
C
V
T
parasitic
V
AIN
0.6 V
(1)
C
ADC
ai14150c
1. Refer to Table 59 for the values of RAIN, RADC and CADC
.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 59 or Figure 60,
depending on whether V
is connected to V
or not. The 10 nF capacitors should be
REF+
DDA
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 59. Power supply and reference decoupling (V not connected to V
)
DDA
REF+
STM32F103xx
V
REF+
(see note 1)
1 µF // 10 nF
V
DDA
SSA
1 µF // 10 nF
V
/V
REF–
(see note 1)
ai14388b
1. VREF+ and VREF– inputs are available only on 100-pin packages.
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Doc ID 14611 Rev 8
STMICROELECTRONICS [ ST ]
