STM32F103xC, STM32F103xD, STM32F103xE
Electrical characteristics
(1) (2)
Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings
Symbol Parameter Min Max
tv(NADV_NE) FSMC_NEx low to FSMC_NADV low
Unit
ns
ns
5
tw(NADV)
FSMC_NADV low time
tHCLK + 1.5
1. CL = 15 pF.
2. Based on characterisation, not tested in production.
Figure 25. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
t
w(NE)
FSMC_NEx
FSMC_NOE
FSMC_NWE
t
t
t
h(NE_NWE)
v(NWE_NE)
w(NWE)
t
tv(A_NE)
h(A_NWE)
FSMC_A[25:0]
Address
tv(BL_NE)
t
h(BL_NWE)
FSMC_NBL[1:0]
NBL
t
t
v(Data_NE)
h(Data_NWE)
Data
FSMC_D[15:0]
t
v(NADV_NE)
t
w(NADV)
(1)
FSMC_NADV
ai14990
1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.
(1)(2)
Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings
Symbol
tw(NE)
tv(NWE_NE)
tw(NWE)
th(NE_NWE)
tv(A_NE)
Parameter
FSMC_NE low time
Min
Max
Unit
3tHCLK – 1
tHCLK – 0.5
tHCLK – 0.5
3tHCLK + 2
tHCLK + 1.5
tHCLK + 1.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
FSMC_NEx low to FSMC_NWE low
FSMC_NWE low time
FSMC_NWE high to FSMC_NE high hold time tHCLK
FSMC_NEx low to FSMC_A valid
7.5
th(A_NWE)
tv(BL_NE)
th(BL_NWE)
tv(Data_NE)
Address hold time after FSMC_NWE high
FSMC_NEx low to FSMC_BL valid
FSMC_BL hold time after FSMC_NWE high
FSMC_NEx low to Data valid
tHCLK
1.5
tHCLK – 0.5
tHCLK + 7
th(Data_NWE) Data hold time after FSMC_NWE high
tHCLK
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