欢迎访问ic37.com |
会员登录 免费注册
发布采购

STM32F103RCT6 参数 Datasheet PDF下载

STM32F103RCT6图片预览
型号: STM32F103RCT6
PDF下载: 下载PDF文件 查看货源
内容描述: 时钟,复位和电源管理 [Clock, reset and supply management]
分类和应用: 时钟
文件页数/大小: 130 页 / 1933 K
品牌: STMICROELECTRONICS [ ST ]
 浏览型号STM32F103RCT6的Datasheet PDF文件第48页浏览型号STM32F103RCT6的Datasheet PDF文件第49页浏览型号STM32F103RCT6的Datasheet PDF文件第50页浏览型号STM32F103RCT6的Datasheet PDF文件第51页浏览型号STM32F103RCT6的Datasheet PDF文件第53页浏览型号STM32F103RCT6的Datasheet PDF文件第54页浏览型号STM32F103RCT6的Datasheet PDF文件第55页浏览型号STM32F103RCT6的Datasheet PDF文件第56页  
Electrical characteristics  
STM32F103xC, STM32F103xD, STM32F103xE  
Typical current consumption  
The MCU is placed under the following conditions:  
All I/O pins are in input mode with a static value at V or V (no load).  
DD SS  
All peripherals are disabled except if it is explicitly mentioned.  
The Flash access time is adjusted to f frequency (0 wait state from 0 to 24 MHz, 1  
HCLK  
wait state from 24 to 48 MHZ and 2 wait states above).  
Ambient temperature and V supply voltage conditions summarized in Table 10.  
DD  
Prefetch is ON (Reminder: this bit must be set before clock setting and bus prescaling)  
When the peripherals are enabled f  
= f  
/4, f  
2 = f  
/2, f  
= f  
/4  
PCLK1  
HCLK  
PCLK  
HCLK  
ADCCLK  
PCLK2  
Table 18. Typical current consumption in Run mode, code with data processing  
running from Flash  
Typ(1)  
Symbol Parameter  
Conditions  
fHCLK  
Unit  
Allperipherals Allperipherals  
enabled(2)  
disabled  
72 MHz  
48 MHz  
36 MHz  
24 MHz  
16 MHz  
8 MHz  
51  
34.6  
26.6  
18.5  
12.8  
7.2  
4.2  
2.7  
2
30.5  
20.7  
16.2  
11.4  
8.2  
5
External clock(3)  
mA  
4 MHz  
3.1  
2.1  
1.7  
1.4  
1.2  
27  
2 MHz  
1 MHz  
500 kHz  
125 kHz  
64 MHz  
48 MHz  
36 MHz  
24 MHz  
16 MHz  
8 MHz  
1.6  
1.3  
45  
Supply  
IDD  
current in  
Run mode  
34  
20.1  
15.6  
10.8  
7.6  
4.4  
2.5  
1.5  
1.1  
0.8  
0.6  
26  
17.9  
12.2  
6.6  
3.6  
2.1  
1.4  
1
Running on high  
speed internal RC  
(HSI), AHB  
prescaler used to  
reduce the  
mA  
4 MHz  
frequency  
2 MHz  
1 MHz  
500 kHz  
125 kHz  
0.7  
1. Typical values are measures at TA = 25 °C, VDD = 3.3 V.  
2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this  
consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).  
3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.  
52/130  
Doc ID 14611 Rev 8