Description
Figure 2.
Clock tree
STM32F103x8, STM32F103xB
FLITFCLK
to Flash programming interface
8 MHz
HSI RC
HSI
/2
USB
Prescaler
/1, 1.5
48 MHz
USBCLK
to USB interface
HCLK
to AHB bus, core,
memory and DMA
to Cortex System timer
FCLK Cortex
free running clock
PCLK1
to APB1
peripherals
Peripheral Clock
Enable (13 bits)
72 MHz max
Clock
Enable (3 bits)
PLLSRC
PLLMUL
..., x16
x2, x3, x4
PLL
HSI
PLLCLK
HSE
SW
SYSCLK
/8
AHB
Prescaler
72 MHz
/1, 2..512
max
APB1
Prescaler
/1, 2, 4, 8, 16
36 MHz max
CSS
to TIM2, 3
TIM2,3, 4
and 4
If (APB1 prescaler =1) x1
TIMXCLK
else
x2
Peripheral Clock
Enable (3 bits)
PLLXTPRE
OSC_OUT
OSC_IN
4-16 MHz
HSE OSC
/2
APB2
Prescaler
/1, 2, 4, 8, 16
72 MHz max
Peripheral Clock
Enable (11 bits)
PCLK2
to APB2
peripherals
TIM1 timer
to TIM1
If (APB2 prescaler =1) x1
TIM1CLK
else
x2
Peripheral Clock
LSE
to RTC
/128
OSC32_IN
OSC32_OUT
LSE OSC
32.768 kHz
ADC
Prescaler
/2, 4, 6, 8
Enable (1 bit)
to ADC
RTCCLK
RTCSEL[1:0]
ADCCLK
LSI RC
40 kHz
LSI
to Independent Watchdog (IWDG)
IWDGCLK
Legend:
Main
Clock Output
/2
PLLCLK
HSI
HSE
SYSCLK
MCO
HSE = high-speed external clock signal
HSI = high-speed internal clock signal
LSI = low-speed internal clock signal
LSE = low-speed external clock signal
MCO
ai14903
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
64 MHz.
2. For the USB function to be available, both HSE and PLL must be enabled, with USBCLK running at 48
MHz.
3. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz, 28 MHz or 56 MHz.
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Doc ID 13587 Rev 14
STMICROELECTRONICS [ STMICROELECTRONICS ]
