Electrical characteristics
STM32F103xx
Figure 17. Recommended NRST pin protection
V
DD
External
reset circuit
R
PU
Internal Reset
NRST
FILTER
0.1 µF
STM32F101xx
ai14132b
2. The reset network protects the device against parasitic resets.
3. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 32. Otherwise the reset will not be taken into account by the device.
5.3.14
TIM timer characteristics
Unless otherwise specified, the parameters given in Table 33 are derived from tests
performed under ambient temperature, f
frequency and V supply voltage conditions
PCLKx
DD
summarized in Table 7.
Refer to Section 5.3.12: I/O port pin characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
(1)
Table 33. TIMx characteristics
Symbol
Parameter
Conditions
Min
1
Max
Unit
tTIMxCLK
tres(TIM)
Timer resolution time
fTIMxCLK = 72 MHz
fTIMxCLK = 72 MHz
13.9
0
ns
MHz
MHz
bit
f
TIMxCLK/2
36
Timer external clock
frequency on CH1 to CH4
fEXT
0
ResTIM
Timer resolution
16
16-bit counter clock period
when internal clock is
selected
tTIMxCLK
1
65536
910
tCOUNTER
fTIMxCLK = 72 MHz
fTIMxCLK = 72 MHz
0.0139
µs
tTIMxCLK
s
65536 × 65536
59.6
tMAX_COUNT
Maximum possible count
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers.
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