Electrical characteristics
STM32F103xx
Wakeup time from low power mode
The wakeup times given in
is measured on a wakeup phase with a 8-MHz HSI RC
oscillator. The clock source used to wake up the device depends from the current operating
mode:
●
●
Stop or Standby mode: the clock source is the RC oscillator
Sleep mode: the clock source is the clock that was set before entering Sleep mode.
All timings are derived from tests performed under ambient temperature and V
DD
supply
voltage conditions summarized in
Table 21.
Symbol
Low-power mode wakeup timings
(1)
Parameter
Conditions
Wakeup on HSI RC clock
HSI RC wakeup time = 2 µs
HSI RC wakeup time = 2 µs,
Regulator wakeup from LP
mode time = 5 µs
HSI RC wakeup time = 2 µs,
Regulator wakeup from power
down time = 38 µs
Typ
0.75
4
Max
TBD
TBD
µs
7
TBD
Unit
µs
t
WUSLEEP(2)
Wakeup from Sleep mode
Wakeup from Stop mode
(regulator in run mode)
t
WUSTOP(2)
Wakeup from Stop mode
(regulator in low power mode)
t
WUSTDBY(3)
Wakeup from Standby mode
40
TBD
µs
1. TBD stands for to be determined.
2. The wakeup time from Sleep and Stop mode are measured from the wakeup event to the point in which the
user application code reads the first instruction.
3. The wakeup time from Standby mode is measured from the wakeup event to the point in which the device
exits from reset.
5.3.8
PLL characteristics
The parameters given in
are derived from tests performed under ambient
temperature and V
DD
supply voltage conditions summarized in
Table 22.
Symbol
PLL characteristics
(1)
Value
Parameter
PLL input clock
Test Conditions
Min
Typ
8.0
40
16
When PLL operates
(locked)
32
60
72
144
200
V
DD
is stable
TBD
TBD
Max
(2)
Unit
MHz
%
MHz
MHz
µs
%
f
PLL_IN
f
PLL_OUT
f
VCO
t
LOCK
t
JITTER
PLL input clock duty cycle
PLL multiplier output clock
VCO frequency range
PLL lock time
Cycle to cycle jitter (+/-3Σ
peak to peak)
1. TBD stands for to be determined.
2. Data based on device characterization, not tested in production.
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