STM32F103xx
Electrical characteristics
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 36 are derived from tests
performed under ambient temperature, f
frequency and V supply voltage conditions
PCLKx
DD
summarized in Table 7.
Refer to Section 5.3.12: I/O port pin characteristics for more details on the input/output
alternate function characteristics (NSS, SCK, MOSI, MISO).
(1)
Table 36. SPI characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
Master mode
Slave mode
TBD
0
TBD
TBD
fSCK
1/tc(SCK)
SPI clock frequency
MHz
tr(SCK)
tf(SCK)
SPI clock rise and fall
time
Capacitive load: C=50 pF
TBD
(2)
tsu(NSS)
NSS setup time
NSS hold time
Slave mode
Slave mode
0
0
(2)
th(NSS)
(2)
tw(SCKH)
tw(SCKL)
SCK high and low
time
Master mode, fPCLK= TBD,
presc = TBD
TBD
(2)
(2)
Master mode
Slave mode
TBD
TBD
tsu(MI)
tsu(SI)
Data input setup time
(2)
Master mode
TBD
(2)
Slave mode
TBD
th(MI)
th(SI)
Data input hold time
(2)
Master mode, fPCLK= TBD
Slave mode, fPCLK= TBD
Slave mode
TBD(3)
TBD(3)
TBD
ns
TBD
TBD
Data output access
time
(2)(4)
(2)(5)
ta(SO)
Slave mode, fPCLK= TBD
TBD
Data output disable
time
tdis(SO)
Slave mode
TBD
TBD
Slave mode (after enable edge)
fPCLK= TBD
TBD
TBD
(2)(1)
tv(SO)
Data output valid time
Data output valid time
Master mode (after enable
edge)
TBD
TBD
(2)(1)
(2)
tv(MO)
fPCLK= TBD
TBD
TBD
th(SO)
Slave mode (after enable edge)
Data output hold time
Master mode (after enable
edge)
(2)
th(MO)
TBD
1. TBD = to be determined.
2. Values based on design simulation and/or characterization results, and not tested in production.
3. Depends on fPCLK. For example, if fPCLK= 8MHz, then tPCLK = 1/fPLCLK =125 ns and tv(MO) = 255 ns.
4. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
5. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
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