EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
Figure 91. Timer Block Diagram
ST9 INTERNAL BUS
INTCLK
MCU-PERIPHERAL INTERFACE
8 low
8-bit
8 high
8
8
8
8
8
8
8
8
buffer
EXEDG
16
INPUT
CAPTURE
REGISTER
INPUT
CAPTURE
REGISTER
OUTPUT
COMPARE
REGISTER
OUTPUT
COMPARE
REGISTER
16 BIT
FREE RUNNING
1/2
1/4
1/8
COUNTER
1
1
2
2
COUNTER
ALTERNATE
REGISTER
16
16
16
CC1 CC0
TIMER INTERNAL BUS
16
16
OVERFLOW
DETECT
CIRCUIT
EXTCLK
EDGE DETECT
CIRCUIT1
OUTPUT COMPARE
CIRCUIT
ICAP1
ICAP2
6
EDGE DETECT
CIRCUIT2
OCMP1
OCMP2
LATCH1
LATCH2
ICF1 OCF1 TOF ICF2 OCF2
0
0
0
SR
EXEDG
ICIE OCIE TOIE FOLV2 FOLV1OLVL2 IEDG1 OLVL1
OC1E
OPM PWM CC1 CC0 IEDG2
OC2E
CR1
CR2
OCF2
OCF1
1
0
EFTIS
IC1IE
IC2IE OC2IE
-
-
-
OC1IE
CR3
ICF1
1
0
ICF2
0
1
INTx External interrupt pin
EFTI Interrupt
Request
167/426
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