ST92F124/F150/F250 - EXTERNAL MEMORY INTERFACE (EXTMI)
EXTERNAL MEMORY SIGNALS (Cont’d)
8.2.8 WAIT: External Memory Wait
cle, WAIT is sampled again to continue or finish
the memory cycle stretching. Note that if WAIT is
sampled active during phase T1 then AS is
stretched, while if WAIT is sampled active during
phase T2 then DS is stretched. WAIT is enabled
via software as the Alternate Function input of the
associated I/O port bit (refer to specific ST9 ver-
sion to identify the specific port and pin). Refer to
Figure 78.
WAIT (Alternate Function Input, Active low) indi-
cates to the ST9 that the external memory requires
more time to complete the memory access cycle. If
bit EWEN (EIVR) is set, the WAIT signal is sam-
pled with the rising edge of the processor internal
clock during phase T1 or T2 of every memory cy-
cle. If the signal was sampled active, one more in-
ternal clock cycle is added to the memory cycle.
On the rising edge of the added internal clock cy-
Figure 78. External memory Read/Write sequence with external wait request (WAIT pin)
T2
T1
T2
T1
T2
T1
WAIT
SYSTEM
CLOCK
ADDRESS
ADDRESS
ADDRESS
P1, P9
AS (MC=0)
ALE (MC=1)
DS (MC=0)
ADD.
ADDRESS
ADD.
D.IN
D.IN
P0
D.IN
RW (MC=0)
OEN (MC=1)
WEN (MC=1)
D.OUT
ADD.
DATA OUT
ADD.
ADDRESS
P0
D.OUT
RW (MC=0)
OEN (MC=1)
WEN (MC=1)
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STMICROELECTRONICS [ ST ]
