ST24/25C16, ST24/25W16
Figure 11. Read Modes Sequence
ACK
NO ACK
DATA OUT
CURRENT
ADDRESS
READ
DEV SEL
R/W
ACK
ACK
ACK
NO ACK
DATA OUT
RANDOM
ADDRESS
READ
DEV SEL *
BYTE ADDR
DEV SEL *
R/W
R/W
ACK
ACK
ACK
NO ACK
SEQUENTIAL
CURRENT
READ
DEV SEL
DATA OUT 1
DATA OUT N
R/W
ACK
ACK
ACK
ACK
SEQUENTIAL
RANDOM
READ
DEV SEL *
BYTE ADDR
DEV SEL * DATA OUT 1
R/W
R/W
ACK
NO ACK
DATA OUT N
AI00794C
Note:
* The 7 Most Significant bits of DEV SEL bytes of a Random Read (1st byte and 3rd byte) must be identical.
put, but MUST generate a STOP condition. The
output data is from consecutive byte addresses,
with the internal byte address counter automat-
ically incremented after each byte output. After a
count of the last memory address, the address
counter will ’roll- over’andthememory willcontinue
to output data.
Acknowledge in Read Mode. In all read modes
the ST24/25x16 wait for an acknowledge during the
9th bit time. If the master does not pull the SDAline
low during this time, the ST24/25x16 terminate the
data transfer and switches to a standby state.
13/17
STMICROELECTRONICS [ ST ]
