Register set
ST10F276E
22.7
X-registers ordered by address
Table 70 lists by order of their physical addresses all X-Bus registers which are implemented
in the ST10F276E. Although also physically mapped on X-Bus memory space, the Flash
control registers are listed in a separate section.
Note:
The X-registers are not bit-addressable.
Table 70. X-registers ordered by address
Physical
Name
Description
Reset value
0000h
address
XSSCCON
E800h
XSSC control register
XSSCCONSET
XSSCCONCLR
XSSCTB
E802h
E804h
E806h
E808h
E80Ah
E880h
E900h
E902h
E904h
E906h
E908h
E90Ah
E980h
EA00h
EA02h
EA04h
EA06h
EA08h
EA0Ah
EA0Ch
EA0Eh
EB02h
EB10h
EB12h
EB14h
EB20h
EB22h
EB24h
XSSC set control register (write-only)
XSSC clear control register (write-only)
XSSC transmit buffer
0000h
0000h
0000h
XXXXh
0000h
0000h
0000h
0000h
0000h
XSSCRB
XSSCBR
XSSCPORT
XS1CON
XS1CONSET
XS1CONCLR
XS1BG
XSSC receive buffer
XSSC baud rate register
XSSC port control register
XASC control register
XASC set control register (write-only)
XASC clear control register (write-only)
XASC baud rate generator reload register 0000h
XS1TBUF
XS1RBUF
XS1PORT
I2CCR
XASC transmit buffer register
XASC receive buffer register
XASC port control register
I2C control register
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
- - 00h
0000h
0000h
0000h
0000h
0000h
0000h
I2CSR1
I2C status register 1
I2CSR2
I2C status register 2
I2CCCR1
I2COAR1
I2COAR2
I2CDR
I2C clock control register 1
I2C own address register 1
I2C own address register 2
I2C data register
I2CCCR2
XCLKOUTDIV
XIR0SEL
XIR0SET
XIR0CLR
XIR1SEL
XIR1SET
XIR1CLR
I2C clock control register 2
CLKOUT divider control register
X-Interrupt 0 selection register
X-Interrupt 0 set register (write-only)
X-Interrupt 0 clear register (write-only)
X-Interrupt 1 selection register
X-Interrupt 1 set register (write-only)
X-Interrupt 1 clear register (write-only)
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Doc ID 12303 Rev 3
STMICROELECTRONICS [ ST ]
