M95040, M95020, M95010
Write Enable (WREN)
As shown in Figure 8., to send this instruction to
the device, Chip Select (S) is driven Low, and the
bits of the instruction byte are shifted in, on Serial
Data Input (D). The device then enters a wait
state. It waits for a the device to be deselected, by
Chip Select (S) being driven High.
The Write Enable Latch (WEL) bit must be set pri-
or to each WRITE and WRSR instruction. The only
way to do this is to send a Write Enable instruction
to the device.
Figure 8. Write Enable (WREN) Sequence
S
0
1
2
3
4
5
6
7
C
D
Q
Instruction
High Impedance
AI01441D
Write Disable (WRDI)
The device then enters a wait state. It waits for a
the device to be deselected, by Chip Select (S) be-
ing driven High.
The Write Enable Latch (WEL) bit, in fact, be-
comes reset by any of the following events:
One way of resetting the Write Enable Latch
(WEL) bit is to send a Write Disable instruction to
the device.
As shown in Figure 9., to send this instruction to
the device, Chip Select (S) is driven Low, and the
bits of the instruction byte are shifted in, on Serial
Data Input (D).
–
–
–
–
–
Power-up
WRDI instruction execution
WRSR instruction completion
WRITE instruction completion
Write Protect (W) line being held Low.
Figure 9. Write Disable (WRDI) Sequence
S
0
1
2
3
4
5
6
7
C
D
Q
Instruction
High Impedance
AI03790D
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STMICROELECTRONICS [ ST ]
