M4T28-BR12SH1 参数 Datasheet PDF下载

M41T94

Figure 4.

Block diagram

E

SDO

SDI

SCL

SPI

INTERFACE

REAL TIME CLOCK

CALENDAR

44 BYTES

USER RAM

RTC w/ALARM

& CALIBRATION

WATCHDOG

SQUARE WAVE

AF

WDF

Description

IRQ/FT/OUT

(1)

Crystal

32KHz

OSCILLATOR

SQW

WDI

VCC

VBAT

VBL= 2.5V

COMPARE

BL

VSO = 2.5V

COMPARE

VPFD = 4.4V

RSTIN1

RSTIN2

COMPARE

(2.65V if THS = VSS)

POR

RST(1)

AI04785

1. Open drain output

Figure 5.

Hardware hookup

SPI Interface with

(CPOL, CPHA)(1) =

('0','0') or ('1','1')

D

Q

C

Master

(ST6, ST7, ST9,

ST10, Others)

CS3

CS2

CS1

C

Q

D

C

Q

XXXXX

D

C

Q

XXXXX

D

M41T94

E

E

E

AI03686

1. CPOL (clock polarity) and CPHA (clock phase) are bits that may be set in the SPI control register of the MCU.

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