M27C4002
Figure 6. Programming and Verify Modes AC Waveforms
A0-A17
tAVEL
Q0-Q15
DATA IN
tQVEL
VPP
tVPHEL
VCC
tVCHEL
E
tELEH
G
VALID
DATA OUT
tEHQX
tGLQV
tGHQZ
tGHAX
tQXGL
PROGRAM
VERIFY
AI00730
Figure 7. Programming Flowchart
VCC = 6.25V, VPP = 12.75V
n=0
E = 100µs Pulse
NO
++n
= 25
YES
NO
VERIFY
YES
Last
Addr
NO
++ Addr
FAIL
YES
CHECK ALL WORDS
1st: VCC = 6V
2nd: VCC = 4.2V
AI00726C
PRESTO II Programming Algorithm
PRESTO II Programming Algorithm allows the
whole array to be programmed with a guaranteed
margin, in a typical time of 26.5 seconds. Pro-
gramming with PRESTO II consists of applying a
sequence of 100µs program pulses to each byte
until a correct verify occurs (see Figure 7). During
programming and verify operation, a MARGIN
MODE circuit is automatically activated in order to
guarantee that each cell is programmed with
enough margin. No overprogram pulse is applied
since the verify in MARGIN MODE provides nec-
essary margin to each programmed cell.
Program Inhibit
Programming of multiple M27C4002s in parallel
with different data is also easily accomplished. Ex-
cept for E, all like inputs including G of the parallel
M27C4002 may be common. A TTL low level
pulse applied to a M27C4002's E input, with V
PP
at 12.75V, will program that M27C4002. A high
level E input inhibits the other M27C4002s from
being programmed.
Program Verify
A verify (read) should be performed on the pro-
grammed bits to determine that they were correct-
ly programmed. The verify is accomplished with G
at V
IL
, E at V
IH
, V
PP
at 12.75V and V
CC
at 6.25V.
9/18
STMICROELECTRONICS [ STMICROELECTRONICS ]
