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M25P40-VMN6TP/X 参数 Datasheet PDF下载

M25P40-VMN6TP/X图片预览
型号: M25P40-VMN6TP/X
PDF下载: 下载PDF文件 查看货源
内容描述: 4兆位,低电压,串行闪存,具有50 MHz SPI总线接口 [4 Mbit, low voltage, serial Flash memory with 50 MHz SPI bus interface]
分类和应用: 闪存
文件页数/大小: 53 页 / 499 K
品牌: STMICROELECTRONICS [ ST ]
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DC and ac parameters  
M25P40  
Table 19. AC characteristics (25 MHz operation, device grade 3, V min = 2.7 V)  
CC  
Test conditions specified in Table 10 and Table 17  
Symbol Alt.  
Parameter  
Min.  
Typ.  
Max.  
Unit  
Clock frequency for the following  
fC  
fR  
fC  
instructions: FAST_READ, PP, SE, BE, DP,  
RES, WREN, WRDI, RDSR, WRSR  
D.C.  
25  
20  
MHz  
Clock frequency for READ instructions  
D.C.  
18  
18  
0.1  
0.1  
10  
10  
5
MHz  
ns  
(1)  
tCH  
tCLH Clock High time  
tCLL Clock Low time  
(1)  
tCL  
ns  
Clock Rise time(3) (peak to peak)  
V/ns  
V/ns  
ns  
(2)  
(2)  
tCLCH  
tCHCL  
Clock Fall time(3) (peak to peak)  
tCSS S Active Setup time (relative to C)  
S Not Active Hold time (relative to C)  
tDSU Data In Setup time  
tSLCH  
tCHSL  
tDVCH  
tCHDX  
tCHSH  
tSHCH  
tSHSL  
ns  
ns  
tDH Data In Hold time  
5
ns  
S Active Hold time (relative to C)  
S Not Active Setup time (relative to C)  
tCSH S Deselect time  
10  
10  
100  
ns  
ns  
ns  
(2)  
tSHQZ  
tCLQV  
tCLQX  
tHLCH  
tCHHH  
tHHCH  
tCHHL  
tDIS Output Disable time  
15  
15  
ns  
tV  
tHO Output Hold time  
HOLD Setup time (relative to C)  
Clock Low to Output Valid  
ns  
0
ns  
10  
10  
10  
10  
ns  
HOLD Hold time (relative to C)  
HOLD Setup time (relative to C)  
HOLD Hold time (relative to C)  
tLZ HOLD to Output Low-Z  
tHZ HOLD to Output High-Z  
Write Protect Setup time  
ns  
ns  
ns  
(2)  
tHHQX  
15  
20  
ns  
(2)  
tHLQZ  
tWHSL  
tSHWL  
ns  
(4)  
(4)  
20  
ns  
Write Protect Hold time  
100  
ns  
(2)  
tDP  
S High to Deep Power-down mode  
3
µs  
S High to Standby Power mode without  
Electronic Signature Read  
(2)  
tRES1  
3 or 30(5)  
µs  
µs  
S High to Standby Power mode with  
Electronic Signature Read  
(2)  
tRES2  
1.8 or 30(5)  
1. tCH + tCL must be greater than or equal to 1/ fC  
2. Value guaranteed by characterization, not 100% tested in production.  
3. Expressed as a slew-rate.  
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.  
5. It is 30 µs in devices produced with the “X” process technology (grade 3 devices are only produced using  
the “X” process technology). Details of how to find the process letter on the device marking are given in the  
Application note AN1995.  
42/53  
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