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M25P40-VMN6TP/X 参数 Datasheet PDF下载

M25P40-VMN6TP/X图片预览
型号: M25P40-VMN6TP/X
PDF下载: 下载PDF文件 查看货源
内容描述: 4兆位,低电压,串行闪存,具有50 MHz SPI总线接口 [4 Mbit, low voltage, serial Flash memory with 50 MHz SPI bus interface]
分类和应用: 闪存
文件页数/大小: 53 页 / 499 K
品牌: STMICROELECTRONICS [ ST ]
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M25P40  
Instructions  
6.12  
Release from Deep Power-down and Read Electronic  
Signature (RES)  
Once the device has entered the Deep Power-down mode, all instructions are ignored  
except the Release from Deep Power-down and Read Electronic Signature (RES)  
instruction. Executing this instruction takes the device out of the Deep Power-down mode.  
The instruction can also be used to read, on Serial Data output (Q), the 8-bit Electronic  
Signature, whose value for the M25P40 is 12h.  
Except while an Erase, Program or Write Status Register cycle is in progress, the Release  
from Deep Power-down and Read Electronic Signature (RES) instruction always provides  
access to the 8-bit Electronic Signature of the device, and can be applied even if the Deep  
Power-down mode has not been entered.  
Any Release from Deep Power-down and Read Electronic Signature (RES) instruction while  
an Erase, Program or Write Status Register cycle is in progress, is not decoded, and has no  
effect on the cycle that is in progress.  
The device is first selected by driving Chip Select (S) Low. The instruction code is followed  
by 3 dummy bytes, each bit being latched-in on Serial Data input (D) during the rising edge  
of Serial Clock (C). Then, the 8-bit Electronic Signature, stored in the memory, is shifted out  
on Serial Data output (Q), each bit being shifted out during the falling edge of Serial Clock  
(C).  
The instruction sequence is shown in Figure 18.  
The Release from Deep Power-down and Read Electronic Signature (RES) instruction is  
terminated by driving Chip Select (S) High after the Electronic Signature has been read at  
least once. Sending additional clock cycles on Serial Clock (C), while Chip Select (S) is  
driven Low, cause the Electronic Signature to be output repeatedly.  
When Chip Select (S) is driven High, the device is put in the Standby Power mode. If the  
device was not previously in the Deep Power-down mode, the transition to the Standby  
Power mode is immediate. If the device was previously in the Deep Power-down mode,  
though, the transition to the Standby Power mode is delayed by t  
, and Chip Select (S)  
RES2  
must remain High for at least t  
(max), as specified in Table 19. Once in the Standby  
RES2  
Power mode, the device waits to be selected, so that it can receive, decode and execute  
instructions.  
Driving Chip Select (S) High after the 8-bit instruction byte has been received by the device,  
but before the whole of the 8-bit Electronic Signature has been transmitted for the first time  
(as shown in Figure 19), still ensures that the device is put into Standby Power mode. If the  
device was not previously in the Deep Power-down mode, the transition to the Standby  
Power mode is immediate. If the device was previously in the Deep Power-down mode,  
though, the transition to the Standby Power mode is delayed by t  
, and Chip Select (S)  
RES1  
must remain High for at least t  
(max), as specified in Table 19. Once in the Standby  
RES1  
Power mode, the device waits to be selected, so that it can receive, decode and execute  
instructions.  
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