M25P10-A
Figure 12. Write Status Register (WRSR) Instruction Sequence
S
0
C
Instruction
Status
Register In
7
High Impedance
Q
AI02282D
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
D
6
5
4
3
2
1
0
MSB
Table 7. Protection Modes
W
Signal
1
0
1
SRWD
Bit
0
0
1
Software
Protected
(SPM)
Mode
Write Protection of the Status
Register
Status Register is Writable (if the
WREN instruction has set the WEL
bit)
The values in the SRWD, BP1 and
BP0 bits can be changed
Status Register is Hardware write
protected
The values in the SRWD, BP1 and
BP0 bits cannot be changed
Memory Content
Protected Area
(1)
Protected against
Page Program, Sector
Erase and Bulk Erase
Unprotected Area
(1)
Ready to accept Page
Program and Sector
Erase instructions
0
1
Hardware
Protected
(HPM)
Protected against
Page Program, Sector
Erase and Bulk Erase
Ready to accept Page
Program and Sector
Erase instructions
Note: 1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in
18/41
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