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M24C64-WMN6TP/B 参数 Datasheet PDF下载

M24C64-WMN6TP/B图片预览
型号: M24C64-WMN6TP/B
PDF下载: 下载PDF文件 查看货源
内容描述: [8KX8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 0.150 INCH, ROHS COMPLIANT, PLASTIC, SOP-8]
分类和应用: 存储内存集成电路光电二极管双倍数据速率可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 26 页 / 396 K
品牌: STMICROELECTRONICS [ STMICROELECTRONICS ]
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M24C64, M24C32
SUMMARY DESCRIPTION
These I
2
C-compatible electrically erasable pro-
grammable memory (EEPROM) devices are orga-
nized as 8192 x 8 bits (M24C64) and 4096 x 8 bits
(M24C32).
Figure 2. Logic Diagram
VCC
Table 2. Signal Names
E0, E1, E2
SDA
SCL
WC
V
CC
Chip Enable
Serial Data
Serial Clock
Write Control
Supply Voltage
Ground
3
E0-E2
SCL
WC
M24C64
M24C32
SDA
V
SS
VSS
AI01844B
I
2
C uses a two-wire serial interface, comprising a
bi-directional data line and a clock line. The devic-
es carry a built-in 4-bit Device Type Identifier code
(1010) in accordance with the I
2
C bus definition.
The device behaves as a slave in the I
2
C protocol,
with all memory operations synchronized by the
serial clock. Read and Write operations are initiat-
ed by a Start condition, generated by the bus mas-
ter. The Start condition is followed by a Device
Select Code and Read/Write bit (RW) (as de-
scribed in
terminated by an acknowl-
edge bit.
When writing data to the memory, the device in-
serts an acknowledge bit during the 9
th
bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.
Power On Reset: V
CC
Lock-Out Write Protect
In order to prevent data corruption and inadvertent
Write operations during Power-up, a Power On
Reset (POR) circuit is included. At Power-up, the
internal reset is held active until V
CC
has reached
the Power On Reset (POR) threshold voltage, and
all operations are disabled – the device will not re-
spond to any command. In the same way, when
V
CC
drops from the operating voltage, below the
Power On Reset (POR) threshold voltage, all op-
erations are disabled and the device will not re-
spond to any command.
A stable and valid V
CC
(as defined in
and
must be applied before applying any
logic signal.
Figure 3. DIP, SO, TSSOP and UFDFPN
Connections
M24C64
M24C32
E0
E1
E2
VSS
1
2
3
4
8
7
6
5
AI01845C
VCC
WC
SCL
SDA
Note: See
section for package dimen-
sions, and how to identify pin-1.
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