M24C64, M24C32
Table 16. AC Characteristics (M24Cxx-6, M24Cxx-W6 and M24Cxx-W3)
Test conditions specified in
and
or
Symbol
f
C
t
CHCL
t
CLCH
t
DL1DL2 2
t
DXCX
t
CLDX
t
CLQX
t
CLQV 3
t
CHDX 1
t
DLCL
t
CHDH
t
DHDL
t
W
Note: 1.
2.
3.
4.
Alt.
f
SCL
t
HIGH
t
LOW
t
F
t
SU:DAT
t
HD:DAT
t
DH
t
AA
t
SU:STA
t
HD:STA
t
SU:STO
t
BUF
t
WR
Clock Frequency
Parameter
Min.
Max.
400
Unit
kHz
ns
ns
Clock Pulse Width High
Clock Pulse Width Low
SDA Fall Time
Data In Set Up Time
Data In Hold Time
Data Out Hold Time
Clock Low to Next Data Valid (Access Time)
Start Condition Set Up Time
Start Condition Hold Time
Stop Condition Set Up Time
Time between Stop Condition and Next Start Condition
Write Time
600
1300
20
100
0
200
200
600
600
600
1300
5 or
4
10
900
300
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
For a reSTART condition, or following a Write cycle.
Sampled only, not 100% tested.
To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
The Write Time of 5 ms only applies to devices bearing the process letter “B” in the package marking (on the top side of the pack-
age), otherwise (for devices bearing the process letter “N”) the Write Time is 10 ms. For further details, please contact your nearest
ST sales office, and ask for a copy of the Product Change Notice PCEE0036.
Table 17. AC Characteristics (M24Cxx-R)
Test conditions specified in
and
Symbol
f
C
t
CHCL
t
CLCH
t
DL1DL2 2
t
DXCX
t
CLDX
t
CLQX
t
CLQV 3
t
CHDX 1
t
DLCL
t
CHDH
t
DHDL
t
W
Alt.
f
SCL
t
HIGH
t
LOW
t
F
t
SU:DAT
t
HD:DAT
t
DH
t
AA
t
SU:STA
t
HD:STA
t
SU:STO
t
BUF
t
WR
Clock Frequency
Clock Pulse Width High
Clock Pulse Width Low
SDA Fall Time
Data In Set Up Time
Data In Hold Time
Data Out Hold Time
Clock Low to Next Data Valid (Access Time)
Start Condition Set Up Time
Start Condition Hold Time
Stop Condition Set Up Time
Time between Stop Condition and Next Start Condition
Write Time
600
1300
20
100
0
200
200
600
600
600
1300
10
900
300
Parameter
Min.
Max.
400
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Note: 1. For a reSTART condition, or following a Write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
18/26
STMICROELECTRONICS [ STMICROELECTRONICS ]
