M24C64, M24C32
Figure 5. Write Mode Sequences with WC=1 (data write inhibited)
WC
ACK
BYTE WRITE
START
DEV SEL
R/W
ACK
ACK
NO ACK
DATA IN
STOP
ACK
ACK
NO ACK
DATA IN 1
DATA IN 2
BYTE ADDR
R/W
BYTE ADDR
NO ACK
STOP
BYTE ADDR
BYTE ADDR
WC
ACK
PAGE WRITE
START
WC (cont'd)
NO ACK
PAGE WRITE
(cont'd)
DEV SEL
DATA IN N
AI01120B
byte address counter (the 5 least significant bits
only) is incremented. The transfer is terminated by
the master generating a STOP condition.
When the master generates a STOP condition im-
mediately after the Ack bit (in the “10
th
bit” time
slot), either at the end of a byte write or a page
write, the internal memory write cycle is triggered.
A STOP condition at any other time does not trig-
ger the internal write cycle.
During the internal write cycle, the SDA input is
disabled internally, and the device does not re-
spond to any requests.
6/19
STMICROELECTRONICS [ STMICROELECTRONICS ]
