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M24C02-WMN6TP/W 参数 Datasheet PDF下载

M24C02-WMN6TP/W图片预览
型号: M24C02-WMN6TP/W
PDF下载: 下载PDF文件 查看货源
内容描述: 16Kbit的, 8Kbit , 4k位, 2Kbit和1K位,串行I²C总线EEPROM [16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial I2C Bus EEPROM]
分类和应用: 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 29 页 / 484 K
品牌: STMICROELECTRONICS [ ST ]
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M24C16, M24C08, M24C04, M24C02, M24C01  
Table 15. AC Characteristics (M24Cxx, Device Grade 6)  
Test conditions specified in Table 8. and Table 5.  
4
4
Symbol  
fC  
Alt.  
fSCL  
Parameter  
Unit  
kHz  
ns  
Min.  
Max.  
Clock Frequency  
400  
tCHCL  
tCLCH  
tHIGH  
tLOW  
tF  
Clock Pulse Width High  
Clock Pulse Width Low  
SDA Fall Time  
600  
1300  
20  
ns  
2
300  
900  
ns  
tDL1DL2  
tDXCX  
tCLDX  
tCLQX  
tSU:DAT  
tHD:DAT  
tDH  
Data In Set Up Time  
Data In Hold Time  
Data Out Hold Time  
100  
0
ns  
ns  
200  
200  
ns  
3
tAA  
Clock Low to Next Data Valid (Access Time)  
ns  
tCLQV  
1
tSU:STA  
tHD:STA  
tSU:STO  
tBUF  
Start Condition Set Up Time  
Start Condition Hold Time  
600  
600  
ns  
ns  
ns  
ns  
ms  
tCHDX  
tDLCL  
tCHDH  
tDHDL  
tW  
Stop Condition Set Up Time  
Time between Stop Condition and Next Start Condition  
Write Time  
600  
1300  
tWR  
5
Note: 1. For a reSTART condition, or following a Write cycle.  
2. Sampled only, not 100% tested.  
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.  
4. This is preliminary data for M24Cxx-Wxx3.  
Table 16. AC Characteristics (M24Cxx, Device Grade 3; M24Cxx-W, Device Grade 6 or 3)  
Test conditions specified in Table 8. and Table 5. or Table 6.  
Symbol  
fC  
Alt.  
fSCL  
Parameter  
Min.  
Max.  
Unit  
kHz  
ns  
Clock Frequency  
400  
tCHCL  
tCLCH  
tHIGH  
tLOW  
tF  
Clock Pulse Width High  
Clock Pulse Width Low  
SDA Fall Time  
600  
1300  
20  
ns  
2
300  
900  
ns  
tDL1DL2  
tDXCX  
tCLDX  
tCLQX  
tSU:DAT  
tHD:DAT  
tDH  
Data In Set Up Time  
Data In Hold Time  
Data Out Hold Time  
100  
0
ns  
ns  
200  
200  
ns  
3
tAA  
Clock Low to Next Data Valid (Access Time)  
ns  
tCLQV  
1
tSU:STA  
tHD:STA  
tSU:STO  
tBUF  
Start Condition Set Up Time  
Start Condition Hold Time  
600  
600  
ns  
ns  
ns  
ns  
ms  
tCHDX  
tDLCL  
tCHDH  
tDHDL  
tW  
Stop Condition Set Up Time  
Time between Stop Condition and Next Start Condition  
Write Time  
600  
1300  
4
tWR  
10 or 5  
Note: 1. For a reSTART condition, or following a Write cycle.  
2. Sampled only, not 100% tested.  
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.  
4. 10ms write time is offered on the standard device. 5ms write time is offered on new products bearing the Process Identification letter  
“W” or “G” on the package, as described in Table 24..  
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